mirror of https://gitlab.com/qemu-project/qemu
target-xtensa: define TLB_TEMPLATE for MMU-less cores
TLB_TEMPLATE macro specifies TLB geometry in the core configuration. Make TLB_TEMPLATE available for region protection core variants, defining 1 way ITLB and DTLB with 8 entries each. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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@ -251,6 +251,8 @@
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.nextint = XCHAL_NUM_EXTINTERRUPTS, \
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.nextint = XCHAL_NUM_EXTINTERRUPTS, \
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.extint = EXTINTS
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.extint = EXTINTS
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#if XCHAL_HAVE_PTP_MMU
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#define TLB_TEMPLATE(ways, refill_way_size, way56) { \
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#define TLB_TEMPLATE(ways, refill_way_size, way56) { \
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.nways = ways, \
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.nways = ways, \
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.way_size = { \
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.way_size = { \
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@ -268,11 +270,23 @@
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#define DTLB(varway56) \
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#define DTLB(varway56) \
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TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
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TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
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#if XCHAL_HAVE_PTP_MMU
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#define TLB_SECTION \
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#define TLB_SECTION \
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.itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
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.itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
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.dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
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.dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
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#else
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#elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
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#define TLB_TEMPLATE { \
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.nways = 1, \
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.way_size = { \
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8, \
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} \
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}
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#define TLB_SECTION \
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.itlb = TLB_TEMPLATE, \
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.dtlb = TLB_TEMPLATE
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#endif
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#endif
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#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
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#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
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