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disas/riscv: enable disassembly for zicfiss instructions

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Enable disassembly for sspush, sspopchk, ssrdp & ssamoswap.
Disasembly is only enabled if zimop and zicfiss ext is set to true.

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241008225010.1861630-19-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Deepak Gupta 2024-10-08 15:50:08 -07:00 committed by Alistair Francis
parent 905c032417
commit b9080d0765
2 changed files with 40 additions and 1 deletions
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40
disas/riscv.c
View File

@ -977,6 +977,11 @@ typedef enum {
rv_op_wrs_sto = 946,
rv_op_wrs_nto = 947,
rv_op_lpad = 948,
rv_op_sspush = 949,
rv_op_sspopchk = 950,
rv_op_ssrdp = 951,
rv_op_ssamoswap_w = 952,
rv_op_ssamoswap_d = 953,
} rv_op;
/* register names */
@ -2238,6 +2243,11 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "wrs.sto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
{ "wrs.nto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
{ "lpad", rv_codec_lp, rv_fmt_imm, NULL, 0, 0, 0 },
{ "sspush", rv_codec_r, rv_fmt_rs2, NULL, 0, 0, 0 },
{ "sspopchk", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
{ "ssrdp", rv_codec_r, rv_fmt_rd, NULL, 0, 0, 0 },
{ "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
{ "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
};
/* CSR names */
@ -2255,6 +2265,7 @@ static const char *csr_name(int csrno)
case 0x0009: return "vxsat";
case 0x000a: return "vxrm";
case 0x000f: return "vcsr";
case 0x0011: return "ssp";
case 0x0015: return "seed";
case 0x0017: return "jvt";
case 0x0040: return "uscratch";
@ -3081,6 +3092,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 66: op = rv_op_amoor_w; break;
case 67: op = rv_op_amoor_d; break;
case 68: op = rv_op_amoor_q; break;
case 74: op = rv_op_ssamoswap_w; break;
case 75: op = rv_op_ssamoswap_d; break;
case 96: op = rv_op_amoand_b; break;
case 97: op = rv_op_amoand_h; break;
case 98: op = rv_op_amoand_w; break;
@ -4034,7 +4047,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 3: op = rv_op_csrrc; break;
case 4:
if (dec->cfg->ext_zimop) {
int imm_mop5, imm_mop3;
int imm_mop5, imm_mop3, reg_num;
if ((extract32(inst, 22, 10) & 0b1011001111)
== 0b1000000111) {
imm_mop5 = deposit32(deposit32(extract32(inst, 20, 2),
@ -4042,11 +4055,36 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
extract32(inst, 26, 2)),
4, 1, extract32(inst, 30, 1));
op = rv_mop_r_0 + imm_mop5;
/* if zicfiss enabled and mop5 is shadow stack */
if (dec->cfg->ext_zicfiss &&
((imm_mop5 & 0b11100) == 0b11100)) {
/* rs1=0 means ssrdp */
if ((inst & (0b011111 << 15)) == 0) {
op = rv_op_ssrdp;
}
/* rd=0 means sspopchk */
reg_num = (inst >> 15) & 0b011111;
if (((inst & (0b011111 << 7)) == 0) &&
((reg_num == 1) || (reg_num == 5))) {
op = rv_op_sspopchk;
}
}
} else if ((extract32(inst, 25, 7) & 0b1011001)
== 0b1000001) {
imm_mop3 = deposit32(extract32(inst, 26, 2),
2, 1, extract32(inst, 30, 1));
op = rv_mop_rr_0 + imm_mop3;
/* if zicfiss enabled and mop3 is shadow stack */
if (dec->cfg->ext_zicfiss &&
((imm_mop3 & 0b111) == 0b111)) {
/* rs1=0 and rd=0 means sspush */
reg_num = (inst >> 20) & 0b011111;
if (((inst & (0b011111 << 15)) == 0) &&
((inst & (0b011111 << 7)) == 0) &&
((reg_num == 1) || (reg_num == 5))) {
op = rv_op_sspush;
}
}
}
}
break;

1
disas/riscv.h
View File

@ -224,6 +224,7 @@ enum {
#define rv_fmt_none "O\t"
#define rv_fmt_rs1 "O\t1"
#define rv_fmt_rs2 "O\t2"
#define rv_fmt_offset "O\to"
#define rv_fmt_pred_succ "O\tp,s"
#define rv_fmt_rs1_rs2 "O\t1,2"