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hw/dispaly/sm501: bugfixes, add sanity checks.

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hw/display: use tracepoints, misc cleanups.
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Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200528-pull-request' into staging

hw/dispaly/sm501: bugfixes, add sanity checks.
hw/display: use tracepoints, misc cleanups.

# gpg: Signature made Thu 28 May 2020 13:35:32 BST
# gpg:                using RSA key 4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138

* remotes/kraxel/tags/vga-20200528-pull-request: (21 commits)
  sm501: Remove obsolete changelog and todo comment
  sm501: Optimize small overlapping blits
  sm501: Replace hand written implementation with pixman where possible
  sm501: Clean up local variables in sm501_2d_operation
  sm501: Use BIT(x) macro to shorten constant
  sm501: Shorten long variable names in sm501_2d_operation
  sm501: Convert printf + abort to qemu_log_mask
  hw/display/pxa2xx_lcd: Replace printf() call by qemu_log_mask()
  hw/display/omap_dss: Replace fprintf() call by qemu_log_mask(LOG_UNIMP)
  hw/display/exynos4210_fimd: Use qemu_log_mask(GUEST_ERROR)
  hw/display/vmware_vga: Let the PCI device own its I/O MemoryRegion
  hw/display/vmware_vga: Replace printf() calls by qemu_log_mask(ERROR)
  hw/display/xlnx_dp: Replace disabled DPRINTF() by error_report()
  hw/display/dpcd: Convert debug printf()s to trace events
  hw/display/dpcd: Fix memory region size
  hw/display/cirrus_vga: Convert debug printf() to trace event
  hw/display/cirrus_vga: Use qemu_log_mask(ERROR) instead of debug printf
  hw/display/cirrus_vga: Use qemu_log_mask(UNIMP) instead of debug printf
  hw/display/cirrus_vga: Convert debug printf() to trace event
  hw/display/cg3: Convert debug printf()s to trace events
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-05-28 18:13:20 +01:00
commit b8bee16e94
11 changed files with 302 additions and 283 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
hw/display/cg3.c
View File

@ -35,6 +35,7 @@
#include "hw/qdev-properties.h" #include "hw/qdev-properties.h"
#include "qemu/log.h" #include "qemu/log.h"
#include "qemu/module.h" #include "qemu/module.h"
#include "trace.h"
/* Change to 1 to enable debugging */ /* Change to 1 to enable debugging */
#define DEBUG_CG3 0 #define DEBUG_CG3 0
@ -63,12 +64,6 @@
#define CG3_VRAM_SIZE 0x100000 #define CG3_VRAM_SIZE 0x100000
#define CG3_VRAM_OFFSET 0x800000 #define CG3_VRAM_OFFSET 0x800000
#define DPRINTF(fmt, ...) do { \
if (DEBUG_CG3) { \
printf("CG3: " fmt , ## __VA_ARGS__); \
} \
} while (0)
#define TYPE_CG3 "cgthree" #define TYPE_CG3 "cgthree"
#define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3) #define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3)
@ -195,7 +190,8 @@ static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)
val = 0; val = 0;
break; break;
} }
DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", val, addr); trace_cg3_read(addr, val, size);
return val; return val;
} }
@ -206,9 +202,7 @@ static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
uint8_t regval; uint8_t regval;
int i; int i;
DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " size %d\n", trace_cg3_write(addr, val, size);
val, addr, size);
switch (addr) { switch (addr) {
case CG3_REG_BT458_ADDR: case CG3_REG_BT458_ADDR:
s->dac_index = val; s->dac_index = val;

93
hw/display/cirrus_vga.c
View File

@ -35,6 +35,7 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/module.h" #include "qemu/module.h"
#include "qemu/units.h" #include "qemu/units.h"
#include "qemu/log.h"
#include "sysemu/reset.h" #include "sysemu/reset.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "trace.h" #include "trace.h"
@ -52,7 +53,6 @@
*/ */
//#define DEBUG_CIRRUS //#define DEBUG_CIRRUS
//#define DEBUG_BITBLT
/*************************************** /***************************************
* *
@ -905,9 +905,8 @@ static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
static int cirrus_bitblt_videotocpu(CirrusVGAState * s) static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
{ {
/* XXX */ /* XXX */
#ifdef DEBUG_BITBLT qemu_log_mask(LOG_UNIMP,
printf("cirrus: bitblt (video to cpu) is not implemented yet\n"); "cirrus: bitblt (video to cpu) is not implemented\n");
#endif
return 0; return 0;
} }
@ -950,9 +949,7 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
s->cirrus_blt_dstaddr &= s->cirrus_addr_mask; s->cirrus_blt_dstaddr &= s->cirrus_addr_mask;
s->cirrus_blt_srcaddr &= s->cirrus_addr_mask; s->cirrus_blt_srcaddr &= s->cirrus_addr_mask;
#ifdef DEBUG_BITBLT trace_vga_cirrus_bitblt_start(blt_rop,
printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
blt_rop,
s->cirrus_blt_mode, s->cirrus_blt_mode,
s->cirrus_blt_modeext, s->cirrus_blt_modeext,
s->cirrus_blt_width, s->cirrus_blt_width,
@ -962,7 +959,6 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
s->cirrus_blt_dstaddr, s->cirrus_blt_dstaddr,
s->cirrus_blt_srcaddr, s->cirrus_blt_srcaddr,
s->vga.gr[0x2f]); s->vga.gr[0x2f]);
#endif
switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) { switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
case CIRRUS_BLTMODE_PIXELWIDTH8: case CIRRUS_BLTMODE_PIXELWIDTH8:
@ -978,9 +974,8 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
s->cirrus_blt_pixelwidth = 4; s->cirrus_blt_pixelwidth = 4;
break; break;
default: default:
#ifdef DEBUG_BITBLT qemu_log_mask(LOG_GUEST_ERROR,
printf("cirrus: bitblt - pixel width is unknown\n"); "cirrus: bitblt - pixel width is unknown\n");
#endif
goto bitblt_ignore; goto bitblt_ignore;
} }
s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK; s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
@ -989,9 +984,8 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC | cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
CIRRUS_BLTMODE_MEMSYSDEST)) CIRRUS_BLTMODE_MEMSYSDEST))
== (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) { == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
#ifdef DEBUG_BITBLT qemu_log_mask(LOG_UNIMP,
printf("cirrus: bitblt - memory-to-memory copy is requested\n"); "cirrus: bitblt - memory-to-memory copy requested\n");
#endif
goto bitblt_ignore; goto bitblt_ignore;
} }
@ -1038,7 +1032,9 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
} else { } else {
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) { if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
if (s->cirrus_blt_pixelwidth > 2) { if (s->cirrus_blt_pixelwidth > 2) {
printf("src transparent without colorexpand must be 8bpp or 16bpp\n"); qemu_log_mask(LOG_GUEST_ERROR,
"cirrus: src transparent without colorexpand "
"must be 8bpp or 16bpp\n");
goto bitblt_ignore; goto bitblt_ignore;
} }
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) { if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
@ -1136,10 +1132,9 @@ static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
ret = 16; ret = 16;
break; /* XGA HiColor */ break; /* XGA HiColor */
default: default:
#ifdef DEBUG_CIRRUS qemu_log_mask(LOG_GUEST_ERROR,
printf("cirrus: invalid DAC value %x in 16bpp\n", "cirrus: invalid DAC value 0x%x in 16bpp\n",
(s->cirrus_hidden_dac_data & 0xf)); (s->cirrus_hidden_dac_data & 0xf));
#endif
ret = 15; /* XXX */ ret = 15; /* XXX */
break; break;
} }
@ -1308,11 +1303,9 @@ static int cirrus_vga_read_sr(CirrusVGAState * s)
#endif #endif
return s->vga.sr[s->vga.sr_index]; return s->vga.sr[s->vga.sr_index];
default: default:
#ifdef DEBUG_CIRRUS qemu_log_mask(LOG_GUEST_ERROR,
printf("cirrus: inport sr_index %02x\n", s->vga.sr_index); "cirrus: inport sr_index 0x%02x\n", s->vga.sr_index);
#endif
return 0xff; return 0xff;
break;
} }
} }
@ -1401,10 +1394,9 @@ static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
cirrus_update_memory_access(s); cirrus_update_memory_access(s);
break; break;
default: default:
#ifdef DEBUG_CIRRUS qemu_log_mask(LOG_GUEST_ERROR,
printf("cirrus: outport sr_index %02x, sr_value %02x\n", "cirrus: outport sr_index 0x%02x, sr_value 0x%02x\n",
s->vga.sr_index, val); s->vga.sr_index, val);
#endif
break; break;
} }
} }
@ -1502,9 +1494,8 @@ static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
if (reg_index < 0x3a) { if (reg_index < 0x3a) {
return s->vga.gr[reg_index]; return s->vga.gr[reg_index];
} else { } else {
#ifdef DEBUG_CIRRUS qemu_log_mask(LOG_GUEST_ERROR,
printf("cirrus: inport gr_index %02x\n", reg_index); "cirrus: inport gr_index 0x%02x\n", reg_index);
#endif
return 0xff; return 0xff;
} }
} }
@ -1512,9 +1503,7 @@ static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
static void static void
cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value) cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
{ {
#if defined(DEBUG_BITBLT) && 0 trace_vga_cirrus_write_gr(reg_index, reg_value);
printf("gr%02x: %02x\n", reg_index, reg_value);
#endif
switch (reg_index) { switch (reg_index) {
case 0x00: // Standard VGA, BGCOLOR 0x000000ff case 0x00: // Standard VGA, BGCOLOR 0x000000ff
s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
@ -1593,10 +1582,9 @@ cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
cirrus_write_bitblt(s, reg_value); cirrus_write_bitblt(s, reg_value);
break; break;
default: default:
#ifdef DEBUG_CIRRUS qemu_log_mask(LOG_GUEST_ERROR,
printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index, "cirrus: outport gr_index 0x%02x, gr_value 0x%02x\n",
reg_value); reg_index, reg_value);
#endif
break; break;
} }
} }
@ -1651,9 +1639,8 @@ static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
return s->vga.ar_index & 0x3f; return s->vga.ar_index & 0x3f;
break; break;
default: default:
#ifdef DEBUG_CIRRUS qemu_log_mask(LOG_GUEST_ERROR,
printf("cirrus: inport cr_index %02x\n", reg_index); "cirrus: inport cr_index 0x%02x\n", reg_index);
#endif
return 0xff; return 0xff;
} }
} }
@ -1724,10 +1711,9 @@ static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
break; break;
case 0x25: // Part Status case 0x25: // Part Status
default: default:
#ifdef DEBUG_CIRRUS qemu_log_mask(LOG_GUEST_ERROR,
printf("cirrus: outport cr_index %02x, cr_value %02x\n", "cirrus: outport cr_index 0x%02x, cr_value 0x%02x\n",
s->vga.cr_index, reg_value); s->vga.cr_index, reg_value);
#endif
break; break;
} }
} }
@ -1837,9 +1823,8 @@ static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
value = cirrus_vga_read_gr(s, 0x31); value = cirrus_vga_read_gr(s, 0x31);
break; break;
default: default:
#ifdef DEBUG_CIRRUS qemu_log_mask(LOG_GUEST_ERROR,
printf("cirrus: mmio read - address 0x%04x\n", address); "cirrus: mmio read - address 0x%04x\n", address);
#endif
break; break;
} }
@ -1949,10 +1934,9 @@ static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
cirrus_vga_write_gr(s, 0x31, value); cirrus_vga_write_gr(s, 0x31, value);
break; break;
default: default:
#ifdef DEBUG_CIRRUS qemu_log_mask(LOG_GUEST_ERROR,
printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n", "cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
address, value); address, value);
#endif
break; break;
} }
} }
@ -2050,9 +2034,8 @@ static uint64_t cirrus_vga_mem_read(void *opaque,
} }
} else { } else {
val = 0xff; val = 0xff;
#ifdef DEBUG_CIRRUS qemu_log_mask(LOG_GUEST_ERROR,
printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr); "cirrus: mem_readb 0x" TARGET_FMT_plx "\n", addr);
#endif
} }
return val; return val;
} }
@ -2115,10 +2098,9 @@ static void cirrus_vga_mem_write(void *opaque,
cirrus_mmio_blt_write(s, addr & 0xff, mem_value); cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
} }
} else { } else {
#ifdef DEBUG_CIRRUS qemu_log_mask(LOG_GUEST_ERROR,
printf("cirrus: mem_writeb " TARGET_FMT_plx " value 0x%02" PRIu64 "\n", addr, "cirrus: mem_writeb 0x" TARGET_FMT_plx " "
mem_value); "value 0x%02" PRIu64 "\n", addr, mem_value);
#endif
} }
} }
@ -2414,6 +2396,9 @@ static uint64_t cirrus_linear_bitblt_read(void *opaque,
/* XXX handle bitblt */ /* XXX handle bitblt */
(void)s; (void)s;
qemu_log_mask(LOG_UNIMP,
"cirrus: linear bitblt is not implemented\n");
return 0xff; return 0xff;
} }

20
hw/display/dpcd.c
View File

@ -1,5 +1,5 @@
/* /*
* dpcd.c * Xilinx Display Port Control Data
* *
* Copyright (C) 2015 : GreenSocs Ltd * Copyright (C) 2015 : GreenSocs Ltd
* http://www.greensocs.com/ , email: info@greensocs.com * http://www.greensocs.com/ , email: info@greensocs.com
@ -32,16 +32,7 @@
#include "hw/misc/auxbus.h" #include "hw/misc/auxbus.h"
#include "migration/vmstate.h" #include "migration/vmstate.h"
#include "hw/display/dpcd.h" #include "hw/display/dpcd.h"
#include "trace.h"
#ifndef DEBUG_DPCD
#define DEBUG_DPCD 0
#endif
#define DPRINTF(fmt, ...) do { \
if (DEBUG_DPCD) { \
qemu_log("dpcd: " fmt, ## __VA_ARGS__); \
} \
} while (0)
#define DPCD_READABLE_AREA 0x600 #define DPCD_READABLE_AREA 0x600
@ -70,8 +61,8 @@ static uint64_t dpcd_read(void *opaque, hwaddr offset, unsigned size)
offset); offset);
ret = 0; ret = 0;
} }
trace_dpcd_read(offset, ret);
DPRINTF("read 0x%" PRIX8 " @0x%" HWADDR_PRIX "\n", ret, offset);
return ret; return ret;
} }
@ -80,8 +71,7 @@ static void dpcd_write(void *opaque, hwaddr offset, uint64_t value,
{ {
DPCDState *e = DPCD(opaque); DPCDState *e = DPCD(opaque);
DPRINTF("write 0x%" PRIX8 " @0x%" HWADDR_PRIX "\n", (uint8_t)value, offset); trace_dpcd_write(offset, value);
if (offset < DPCD_READABLE_AREA) { if (offset < DPCD_READABLE_AREA) {
e->dpcd_info[offset] = value; e->dpcd_info[offset] = value;
} else { } else {
@ -137,7 +127,7 @@ static void dpcd_init(Object *obj)
{ {
DPCDState *s = DPCD(obj); DPCDState *s = DPCD(obj);
memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x7FFFF); memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x80000);
aux_init_mmio(AUX_SLAVE(obj), &s->iomem); aux_init_mmio(AUX_SLAVE(obj), &s->iomem);
} }

44
hw/display/exynos4210_fimd.c
View File

@ -31,6 +31,7 @@
#include "ui/pixel_ops.h" #include "ui/pixel_ops.h"
#include "qemu/bswap.h" #include "qemu/bswap.h"
#include "qemu/module.h" #include "qemu/module.h"
#include "qemu/log.h"
/* Debug messages configuration */ /* Debug messages configuration */
#define EXYNOS4210_FIMD_DEBUG 0 #define EXYNOS4210_FIMD_DEBUG 0
@ -39,20 +40,15 @@
#if EXYNOS4210_FIMD_DEBUG == 0 #if EXYNOS4210_FIMD_DEBUG == 0
#define DPRINT_L1(fmt, args...) do { } while (0) #define DPRINT_L1(fmt, args...) do { } while (0)
#define DPRINT_L2(fmt, args...) do { } while (0) #define DPRINT_L2(fmt, args...) do { } while (0)
#define DPRINT_ERROR(fmt, args...) do { } while (0)
#elif EXYNOS4210_FIMD_DEBUG == 1 #elif EXYNOS4210_FIMD_DEBUG == 1
#define DPRINT_L1(fmt, args...) \ #define DPRINT_L1(fmt, args...) \
do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0) do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
#define DPRINT_L2(fmt, args...) do { } while (0) #define DPRINT_L2(fmt, args...) do { } while (0)
#define DPRINT_ERROR(fmt, args...) \
do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
#else #else
#define DPRINT_L1(fmt, args...) \ #define DPRINT_L1(fmt, args...) \
do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0) do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
#define DPRINT_L2(fmt, args...) \ #define DPRINT_L2(fmt, args...) \
do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0) do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
#define DPRINT_ERROR(fmt, args...) \
do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
#endif #endif
#if EXYNOS4210_FIMD_MODE_TRACE == 0 #if EXYNOS4210_FIMD_MODE_TRACE == 0
@ -1108,7 +1104,7 @@ static inline int fimd_get_buffer_id(Exynos4210fimdWindow *w)
case FIMD_WINCON_BUF2_STAT: case FIMD_WINCON_BUF2_STAT:
return 2; return 2;
default: default:
DPRINT_ERROR("Non-existent buffer index\n"); qemu_log_mask(LOG_GUEST_ERROR, "FIMD: Non-existent buffer index\n");
return 0; return 0;
} }
} }
@ -1160,19 +1156,23 @@ static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
if (int128_get64(w->mem_section.size) != w->fb_len || if (int128_get64(w->mem_section.size) != w->fb_len ||
!memory_region_is_ram(w->mem_section.mr)) { !memory_region_is_ram(w->mem_section.mr)) {
DPRINT_ERROR("Failed to find window %u framebuffer region\n", win); qemu_log_mask(LOG_GUEST_ERROR,
"FIMD: Failed to find window %u framebuffer region\n",
win);
goto error_return; goto error_return;
} }
w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len, w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len,
false); false);
if (!w->host_fb_addr) { if (!w->host_fb_addr) {
DPRINT_ERROR("Failed to map window %u framebuffer\n", win); qemu_log_mask(LOG_GUEST_ERROR,
"FIMD: Failed to map window %u framebuffer\n", win);
goto error_return; goto error_return;
} }
if (fb_mapped_len != w->fb_len) { if (fb_mapped_len != w->fb_len) {
DPRINT_ERROR("Window %u mapped framebuffer length is less then " qemu_log_mask(LOG_GUEST_ERROR,
"FIMD: Window %u mapped framebuffer length is less than "
"expected\n", win); "expected\n", win);
cpu_physical_memory_unmap(w->host_fb_addr, fb_mapped_len, 0, 0); cpu_physical_memory_unmap(w->host_fb_addr, fb_mapped_len, 0, 0);
goto error_return; goto error_return;
@ -1490,7 +1490,9 @@ static void exynos4210_fimd_write(void *opaque, hwaddr offset,
break; break;
case 3: case 3:
if (w != 1 && w != 2) { if (w != 1 && w != 2) {
DPRINT_ERROR("Bad write offset 0x%08x\n", offset); qemu_log_mask(LOG_GUEST_ERROR,
"FIMD: Bad write offset 0x%08"HWADDR_PRIx"\n",
offset);
return; return;
} }
s->window[w].osdsize = val; s->window[w].osdsize = val;
@ -1624,7 +1626,9 @@ static void exynos4210_fimd_write(void *opaque, hwaddr offset,
break; break;
case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2: case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2:
if (offset & 0x0004) { if (offset & 0x0004) {
DPRINT_ERROR("bad write offset 0x%08x\n", offset); qemu_log_mask(LOG_GUEST_ERROR,
"FIMD: bad write offset 0x%08"HWADDR_PRIx"\n",
offset);
break; break;
} }
w = (offset - FIMD_VIDW0ADD0_B2) >> 3; w = (offset - FIMD_VIDW0ADD0_B2) >> 3;
@ -1638,14 +1642,18 @@ static void exynos4210_fimd_write(void *opaque, hwaddr offset,
break; break;
case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END: case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END:
if (offset & 0x0004) { if (offset & 0x0004) {
DPRINT_ERROR("bad write offset 0x%08x\n", offset); qemu_log_mask(LOG_GUEST_ERROR,
"FIMD: bad write offset 0x%08"HWADDR_PRIx"\n",
offset);
break; break;
} }
s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start = val; s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start = val;
break; break;
case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END: case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END:
if (offset & 0x0004) { if (offset & 0x0004) {
DPRINT_ERROR("bad write offset 0x%08x\n", offset); qemu_log_mask(LOG_GUEST_ERROR,
"FIMD: bad write offset 0x%08"HWADDR_PRIx"\n",
offset);
break; break;
} }
s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end = val; s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end = val;
@ -1665,7 +1673,8 @@ static void exynos4210_fimd_write(void *opaque, hwaddr offset,
s->window[w].palette[i] = val; s->window[w].palette[i] = val;
break; break;
default: default:
DPRINT_ERROR("bad write offset 0x%08x\n", offset); qemu_log_mask(LOG_GUEST_ERROR,
"FIMD: bad write offset 0x%08"HWADDR_PRIx"\n", offset);
break; break;
} }
} }
@ -1715,7 +1724,9 @@ static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset,
break; break;
case 3: case 3:
if (w != 1 && w != 2) { if (w != 1 && w != 2) {
DPRINT_ERROR("bad read offset 0x%08x\n", offset); qemu_log_mask(LOG_GUEST_ERROR,
"FIMD: bad read offset 0x%08"HWADDR_PRIx"\n",
offset);
return 0xBAADBAAD; return 0xBAADBAAD;
} }
ret = s->window[w].osdsize; ret = s->window[w].osdsize;
@ -1809,7 +1820,8 @@ static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset,
return s->window[w].palette[i]; return s->window[w].palette[i];
} }
DPRINT_ERROR("bad read offset 0x%08x\n", offset); qemu_log_mask(LOG_GUEST_ERROR,
"FIMD: bad read offset 0x%08"HWADDR_PRIx"\n", offset);
return 0xBAADBAAD; return 0xBAADBAAD;
} }

2
hw/display/omap_dss.c
View File

@ -619,7 +619,7 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
if (s->rfbi.control & (1 << 1)) { /* BYPASS */ if (s->rfbi.control & (1 << 1)) { /* BYPASS */
/* TODO: in non-Bypass mode we probably need to just assert the /* TODO: in non-Bypass mode we probably need to just assert the
* DRQ and wait for DMA to write the pixels. */ * DRQ and wait for DMA to write the pixels. */
fprintf(stderr, "%s: Bypass mode unimplemented\n", __func__); qemu_log_mask(LOG_UNIMP, "%s: Bypass mode unimplemented\n", __func__);
return; return;
} }

26
hw/display/pxa2xx_lcd.c
View File

@ -426,9 +426,10 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB)) if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
s->status[0] |= LCSR0_QD; s->status[0] |= LCSR0_QD;
if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT)) if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT)) {
printf("%s: internal frame buffer unsupported\n", __func__); qemu_log_mask(LOG_UNIMP,
"%s: internal frame buffer unsupported\n", __func__);
}
if ((s->control[3] & LCCR3_API) && if ((s->control[3] & LCCR3_API) &&
(value & LCCR0_ENB) && !(value & LCCR0_LCDT)) (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
s->status[0] |= LCSR0_ABC; s->status[0] |= LCSR0_ABC;
@ -462,9 +463,9 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
break; break;
case OVL1C1: case OVL1C1:
if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) {
printf("%s: Overlay 1 not supported\n", __func__); qemu_log_mask(LOG_UNIMP, "%s: Overlay 1 not supported\n", __func__);
}
s->ovl1c[0] = value & 0x80ffffff; s->ovl1c[0] = value & 0x80ffffff;
s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS); s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
break; break;
@ -474,9 +475,9 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
break; break;
case OVL2C1: case OVL2C1:
if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) {
printf("%s: Overlay 2 not supported\n", __func__); qemu_log_mask(LOG_UNIMP, "%s: Overlay 2 not supported\n", __func__);
}
s->ovl2c[0] = value & 0x80ffffff; s->ovl2c[0] = value & 0x80ffffff;
s->dma_ch[2].up = !!(value & OVLC1_EN); s->dma_ch[2].up = !!(value & OVLC1_EN);
s->dma_ch[3].up = !!(value & OVLC1_EN); s->dma_ch[3].up = !!(value & OVLC1_EN);
@ -488,9 +489,10 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
break; break;
case CCR: case CCR:
if (!(s->ccr & CCR_CEN) && (value & CCR_CEN)) if (!(s->ccr & CCR_CEN) && (value & CCR_CEN)) {
printf("%s: Hardware cursor unimplemented\n", __func__); qemu_log_mask(LOG_UNIMP,
"%s: Hardware cursor unimplemented\n", __func__);
}
s->ccr = value & 0x81ffffe7; s->ccr = value & 0x81ffffe7;
s->dma_ch[5].up = !!(value & CCR_CEN); s->dma_ch[5].up = !!(value & CCR_CEN);
break; break;

299
hw/display/sm501.c
View File

@ -2,7 +2,7 @@
* QEMU SM501 Device * QEMU SM501 Device
* *
* Copyright (c) 2008 Shin-ichiro KAWASAKI * Copyright (c) 2008 Shin-ichiro KAWASAKI
* Copyright (c) 2016 BALATON Zoltan * Copyright (c) 2016-2020 BALATON Zoltan
* *
* Permission is hereby granted, free of charge, to any person obtaining a copy * Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal * of this software and associated documentation files (the "Software"), to deal
@ -40,23 +40,6 @@
#include "ui/pixel_ops.h" #include "ui/pixel_ops.h"
#include "qemu/bswap.h" #include "qemu/bswap.h"
/*
* Status: 2010/05/07
* - Minimum implementation for Linux console : mmio regs and CRT layer.
* - 2D graphics acceleration partially supported : only fill rectangle.
*
* Status: 2016/12/04
* - Misc fixes: endianness, hardware cursor
* - Panel support
*
* TODO:
* - Touch panel support
* - USB support
* - UART support
* - More 2D graphics engine support
* - Performance tuning
*/
/*#define DEBUG_SM501*/ /*#define DEBUG_SM501*/
/*#define DEBUG_BITBLT*/ /*#define DEBUG_BITBLT*/
@ -699,139 +682,176 @@ static inline void hwc_invalidate(SM501State *s, int crt)
static void sm501_2d_operation(SM501State *s) static void sm501_2d_operation(SM501State *s)
{ {
/* obtain operation parameters */ int cmd = (s->twoD_control >> 16) & 0x1F;
int operation = (s->twoD_control >> 16) & 0x1f; int rtl = s->twoD_control & BIT(27);
int rtl = s->twoD_control & 0x8000000; int format = (s->twoD_stretch >> 20) & 0x3;
int src_x = (s->twoD_source >> 16) & 0x01FFF;
int src_y = s->twoD_source & 0xFFFF;
int dst_x = (s->twoD_destination >> 16) & 0x01FFF;
int dst_y = s->twoD_destination & 0xFFFF;
int operation_width = (s->twoD_dimension >> 16) & 0x1FFF;
int operation_height = s->twoD_dimension & 0xFFFF;
uint32_t color = s->twoD_foreground;
int format_flags = (s->twoD_stretch >> 20) & 0x3;
int addressing = (s->twoD_stretch >> 16) & 0xF;
int rop_mode = (s->twoD_control >> 15) & 0x1; /* 1 for rop2, else rop3 */ int rop_mode = (s->twoD_control >> 15) & 0x1; /* 1 for rop2, else rop3 */
/* 1 if rop2 source is the pattern, otherwise the source is the bitmap */ /* 1 if rop2 source is the pattern, otherwise the source is the bitmap */
int rop2_source_is_pattern = (s->twoD_control >> 14) & 0x1; int rop2_source_is_pattern = (s->twoD_control >> 14) & 0x1;
int rop = s->twoD_control & 0xFF; int rop = s->twoD_control & 0xFF;
uint32_t src_base = s->twoD_source_base & 0x03FFFFFF; unsigned int dst_x = (s->twoD_destination >> 16) & 0x01FFF;
unsigned int dst_y = s->twoD_destination & 0xFFFF;
unsigned int width = (s->twoD_dimension >> 16) & 0x1FFF;
unsigned int height = s->twoD_dimension & 0xFFFF;
uint32_t dst_base = s->twoD_destination_base & 0x03FFFFFF; uint32_t dst_base = s->twoD_destination_base & 0x03FFFFFF;
unsigned int dst_pitch = (s->twoD_pitch >> 16) & 0x1FFF;
/* get frame buffer info */
uint8_t *src = s->local_mem + src_base;
uint8_t *dst = s->local_mem + dst_base;
int src_width = s->twoD_pitch & 0x1FFF;
int dst_width = (s->twoD_pitch >> 16) & 0x1FFF;
int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0; int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0;
int fb_len = get_width(s, crt) * get_height(s, crt) * get_bpp(s, crt); int fb_len = get_width(s, crt) * get_height(s, crt) * get_bpp(s, crt);
if (addressing != 0x0) { if ((s->twoD_stretch >> 16) & 0xF) {
printf("%s: only XY addressing is supported.\n", __func__); qemu_log_mask(LOG_UNIMP, "sm501: only XY addressing is supported.\n");
abort(); return;
} }
if (rop_mode == 0) { if (s->twoD_source_base & BIT(27) || s->twoD_destination_base & BIT(27)) {
if (rop != 0xcc) { qemu_log_mask(LOG_UNIMP, "sm501: only local memory is supported.\n");
/* Anything other than plain copies are not supported */ return;
qemu_log_mask(LOG_UNIMP, "sm501: rop3 mode with rop %x is not "
"supported.\n", rop);
}
} else {
if (rop2_source_is_pattern && rop != 0x5) {
/* For pattern source, we support only inverse dest */
qemu_log_mask(LOG_UNIMP, "sm501: rop2 source being the pattern and "
"rop %x is not supported.\n", rop);
} else {
if (rop != 0x5 && rop != 0xc) {
/* Anything other than plain copies or inverse dest is not
* supported */
qemu_log_mask(LOG_UNIMP, "sm501: rop mode %x is not "
"supported.\n", rop);
}
}
} }
if ((s->twoD_source_base & 0x08000000) || if (!dst_pitch) {
(s->twoD_destination_base & 0x08000000)) { qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero dest pitch.\n");
printf("%s: only local memory is supported.\n", __func__); return;
abort();
} }
switch (operation) { if (!width || !height) {
case 0x00: /* copy area */ qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero size 2D op.\n");
#define COPY_AREA(_bpp, _pixel_type, rtl) { \ return;
int y, x, index_d, index_s; \
for (y = 0; y < operation_height; y++) { \
for (x = 0; x < operation_width; x++) { \
_pixel_type val; \
\
if (rtl) { \
index_s = ((src_y - y) * src_width + src_x - x) * _bpp; \
index_d = ((dst_y - y) * dst_width + dst_x - x) * _bpp; \
} else { \
index_s = ((src_y + y) * src_width + src_x + x) * _bpp; \
index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
} \
if (rop_mode == 1 && rop == 5) { \
/* Invert dest */ \
val = ~*(_pixel_type *)&dst[index_d]; \
} else { \
val = *(_pixel_type *)&src[index_s]; \
} \
*(_pixel_type *)&dst[index_d] = val; \
} \
} \
} }
switch (format_flags) {
if (rtl) {
dst_x -= width - 1;
dst_y -= height - 1;
}
if (dst_base >= get_local_mem_size(s) || dst_base +
(dst_x + width + (dst_y + height) * (dst_pitch + width)) *
(1 << format) >= get_local_mem_size(s)) {
qemu_log_mask(LOG_GUEST_ERROR, "sm501: 2D op dest is outside vram.\n");
return;
}
switch (cmd) {
case 0: /* BitBlt */
{
static uint32_t tmp_buf[16384];
unsigned int src_x = (s->twoD_source >> 16) & 0x01FFF;
unsigned int src_y = s->twoD_source & 0xFFFF;
uint32_t src_base = s->twoD_source_base & 0x03FFFFFF;
unsigned int src_pitch = s->twoD_pitch & 0x1FFF;
if (!src_pitch) {
qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero src pitch.\n");
return;
}
if (rtl) {
src_x -= width - 1;
src_y -= height - 1;
}
if (src_base >= get_local_mem_size(s) || src_base +
(src_x + width + (src_y + height) * (src_pitch + width)) *
(1 << format) >= get_local_mem_size(s)) {
qemu_log_mask(LOG_GUEST_ERROR,
"sm501: 2D op src is outside vram.\n");
return;
}
if ((rop_mode && rop == 0x5) || (!rop_mode && rop == 0x55)) {
/* Invert dest, is there a way to do this with pixman? */
unsigned int x, y, i;
uint8_t *d = s->local_mem + dst_base;
for (y = 0; y < height; y++) {
i = (dst_x + (dst_y + y) * dst_pitch) * (1 << format);
for (x = 0; x < width; x++, i += (1 << format)) {
switch (format) {
case 0: case 0:
COPY_AREA(1, uint8_t, rtl); d[i] = ~d[i];
break; break;
case 1: case 1:
COPY_AREA(2, uint16_t, rtl); *(uint16_t *)&d[i] = ~*(uint16_t *)&d[i];
break; break;
case 2: case 2:
COPY_AREA(4, uint32_t, rtl); *(uint32_t *)&d[i] = ~*(uint32_t *)&d[i];
break; break;
} }
break;
case 0x01: /* fill rectangle */
#define FILL_RECT(_bpp, _pixel_type) { \
int y, x; \
for (y = 0; y < operation_height; y++) { \
for (x = 0; x < operation_width; x++) { \
int index = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
*(_pixel_type *)&dst[index] = (_pixel_type)color; \
} \
} \
} }
}
} else {
/* Do copy src for unimplemented ops, better than unpainted area */
if ((rop_mode && (rop != 0xc || rop2_source_is_pattern)) ||
(!rop_mode && rop != 0xcc)) {
qemu_log_mask(LOG_UNIMP,
"sm501: rop%d op %x%s not implemented\n",
(rop_mode ? 2 : 3), rop,
(rop2_source_is_pattern ?
" with pattern source" : ""));
}
/* Check for overlaps, this could be made more exact */
uint32_t sb, se, db, de;
sb = src_base + src_x + src_y * (width + src_pitch);
se = sb + width + height * (width + src_pitch);
db = dst_base + dst_x + dst_y * (width + dst_pitch);
de = db + width + height * (width + dst_pitch);
if (rtl && ((db >= sb && db <= se) || (de >= sb && de <= se))) {
/* regions may overlap: copy via temporary */
int free_buf = 0, llb = width * (1 << format);
int tmp_stride = DIV_ROUND_UP(llb, sizeof(uint32_t));
uint32_t *tmp = tmp_buf;
switch (format_flags) { if (tmp_stride * sizeof(uint32_t) * height > sizeof(tmp_buf)) {
case 0: tmp = g_malloc(tmp_stride * sizeof(uint32_t) * height);
FILL_RECT(1, uint8_t); free_buf = 1;
}
pixman_blt((uint32_t *)&s->local_mem[src_base], tmp,
src_pitch * (1 << format) / sizeof(uint32_t),
tmp_stride, 8 * (1 << format), 8 * (1 << format),
src_x, src_y, 0, 0, width, height);
pixman_blt(tmp, (uint32_t *)&s->local_mem[dst_base],
tmp_stride,
dst_pitch * (1 << format) / sizeof(uint32_t),
8 * (1 << format), 8 * (1 << format),
0, 0, dst_x, dst_y, width, height);
if (free_buf) {
g_free(tmp);
}
} else {
pixman_blt((uint32_t *)&s->local_mem[src_base],
(uint32_t *)&s->local_mem[dst_base],
src_pitch * (1 << format) / sizeof(uint32_t),
dst_pitch * (1 << format) / sizeof(uint32_t),
8 * (1 << format), 8 * (1 << format),
src_x, src_y, dst_x, dst_y, width, height);
}
}
break; break;
case 1: }
color = cpu_to_le16(color); case 1: /* Rectangle Fill */
FILL_RECT(2, uint16_t); {
break; uint32_t color = s->twoD_foreground;
case 2:
if (format == 2) {
color = cpu_to_le32(color); color = cpu_to_le32(color);
FILL_RECT(4, uint32_t); } else if (format == 1) {
color = cpu_to_le16(color);
}
pixman_fill((uint32_t *)&s->local_mem[dst_base],
dst_pitch * (1 << format) / sizeof(uint32_t),
8 * (1 << format), dst_x, dst_y, width, height, color);
break; break;
} }
break;
default: default:
printf("non-implemented SM501 2D operation. %d\n", operation); qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2D operation: %d\n",
abort(); cmd);
break; return;
} }
if (dst_base >= get_fb_addr(s, crt) && if (dst_base >= get_fb_addr(s, crt) &&
dst_base <= get_fb_addr(s, crt) + fb_len) { dst_base <= get_fb_addr(s, crt) + fb_len) {
int dst_len = MIN(fb_len, ((dst_y + operation_height - 1) * dst_width + int dst_len = MIN(fb_len, ((dst_y + height - 1) * dst_pitch +
dst_x + operation_width) * (1 << format_flags)); dst_x + width) * (1 << format));
if (dst_len) { if (dst_len) {
memory_region_set_dirty(&s->local_mem_region, dst_base, dst_len); memory_region_set_dirty(&s->local_mem_region, dst_base, dst_len);
} }
@ -892,9 +912,8 @@ static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
break; break;
default: default:
printf("sm501 system config : not implemented register read." qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config"
" addr=%x\n", (int)addr); "register read. addr=%" HWADDR_PRIx "\n", addr);
abort();
} }
return ret; return ret;
@ -948,15 +967,15 @@ static void sm501_system_config_write(void *opaque, hwaddr addr,
break; break;
case SM501_ENDIAN_CONTROL: case SM501_ENDIAN_CONTROL:
if (value & 0x00000001) { if (value & 0x00000001) {
printf("sm501 system config : big endian mode not implemented.\n"); qemu_log_mask(LOG_UNIMP, "sm501: system config big endian mode not"
abort(); " implemented.\n");
} }
break; break;
default: default:
printf("sm501 system config : not implemented register write." qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config"
" addr=%x, val=%x\n", (int)addr, (uint32_t)value); "register write. addr=%" HWADDR_PRIx
abort(); ", val=%" PRIx64 "\n", addr, value);
} }
} }
@ -1207,9 +1226,8 @@ static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
break; break;
default: default:
printf("sm501 disp ctrl : not implemented register read." qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register "
" addr=%x\n", (int)addr); "read. addr=%" HWADDR_PRIx "\n", addr);
abort();
} }
return ret; return ret;
@ -1345,9 +1363,9 @@ static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
break; break;
default: default:
printf("sm501 disp ctrl : not implemented register write." qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register "
" addr=%x, val=%x\n", (int)addr, (unsigned)value); "write. addr=%" HWADDR_PRIx
abort(); ", val=%" PRIx64 "\n", addr, value);
} }
} }
@ -1433,9 +1451,8 @@ static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
ret = 0; /* Should return interrupt status */ ret = 0; /* Should return interrupt status */
break; break;
default: default:
printf("sm501 disp ctrl : not implemented register read." qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register "
" addr=%x\n", (int)addr); "read. addr=%" HWADDR_PRIx "\n", addr);
abort();
} }
return ret; return ret;
@ -1520,9 +1537,9 @@ static void sm501_2d_engine_write(void *opaque, hwaddr addr,
/* ignored, writing 0 should clear interrupt status */ /* ignored, writing 0 should clear interrupt status */
break; break;
default: default:
printf("sm501 2d engine : not implemented register write." qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2d engine register "
" addr=%x, val=%x\n", (int)addr, (unsigned)value); "write. addr=%" HWADDR_PRIx
abort(); ", val=%" PRIx64 "\n", addr, value);
} }
} }
@ -1670,9 +1687,9 @@ static void sm501_update_display(void *opaque)
draw_line = draw_line32_funcs[dst_depth_index]; draw_line = draw_line32_funcs[dst_depth_index];
break; break;
default: default:
printf("sm501 update display : invalid control register value.\n"); qemu_log_mask(LOG_GUEST_ERROR, "sm501: update display"
abort(); "invalid control register value.\n");
break; return;
} }
/* set up to draw hardware cursor */ /* set up to draw hardware cursor */

10
hw/display/trace-events
View File

@ -133,6 +133,8 @@ vga_vbe_write(uint32_t index, uint32_t val) "index 0x%x, val 0x%x"
vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x" vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x" vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x" vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
vga_cirrus_write_gr(uint8_t index, uint8_t val) "GR addr 0x%02x, val 0x%02x"
vga_cirrus_bitblt_start(uint8_t blt_rop, uint8_t blt_mode, uint8_t blt_modeext, int blt_width, int blt_height, int blt_dstpitch, int blt_srcpitch, uint32_t blt_dstaddr, uint32_t blt_srcaddr, uint8_t gr_val) "rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08"PRIx32" saddr=0x%08"PRIx32" writemask=0x%02x"
# sii9022.c # sii9022.c
sii9022_read_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x" sii9022_read_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
@ -151,3 +153,11 @@ artist_vram_write(unsigned int size, uint64_t addr, uint64_t val) "%u 0x%"PRIx64
artist_fill_window(unsigned int start_x, unsigned int start_y, unsigned int width, unsigned int height, uint32_t op, uint32_t ctlpln) "start=%ux%u length=%ux%u op=0x%08x ctlpln=0x%08x" artist_fill_window(unsigned int start_x, unsigned int start_y, unsigned int width, unsigned int height, uint32_t op, uint32_t ctlpln) "start=%ux%u length=%ux%u op=0x%08x ctlpln=0x%08x"
artist_block_move(unsigned int start_x, unsigned int start_y, unsigned int dest_x, unsigned int dest_y, unsigned int width, unsigned int height) "source %ux%u -> dest %ux%u size %ux%u" artist_block_move(unsigned int start_x, unsigned int start_y, unsigned int dest_x, unsigned int dest_y, unsigned int width, unsigned int height) "source %ux%u -> dest %ux%u size %ux%u"
artist_draw_line(unsigned int start_x, unsigned int start_y, unsigned int end_x, unsigned int end_y) "%ux%u %ux%u" artist_draw_line(unsigned int start_x, unsigned int start_y, unsigned int end_x, unsigned int end_y) "%ux%u %ux%u"
# cg3.c
cg3_read(uint32_t addr, uint32_t val, unsigned size) "read addr:0x%06"PRIx32" val:0x%08"PRIx32" size:%u"
cg3_write(uint32_t addr, uint32_t val, unsigned size) "write addr:0x%06"PRIx32" val:0x%08"PRIx32" size:%u"
# dpcd.c
dpcd_read(uint32_t addr, uint8_t val) "read addr:0x%"PRIx32" val:0x%02x"
dpcd_write(uint32_t addr, uint8_t val) "write addr:0x%"PRIx32" val:0x%02x"

18
hw/display/vmware_vga.c
View File

@ -26,6 +26,7 @@
#include "qemu/module.h" #include "qemu/module.h"
#include "qemu/units.h" #include "qemu/units.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu/log.h"
#include "hw/loader.h" #include "hw/loader.h"
#include "trace.h" #include "trace.h"
#include "ui/vnc.h" #include "ui/vnc.h"
@ -953,7 +954,8 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
ret = s->scratch[s->index - SVGA_SCRATCH_BASE]; ret = s->scratch[s->index - SVGA_SCRATCH_BASE];
break; break;
} }
printf("%s: Bad register %02x\n", __func__, s->index); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad register %02x\n", __func__, s->index);
ret = 0; ret = 0;
break; break;
} }
@ -1002,7 +1004,8 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
s->new_width = value; s->new_width = value;
s->invalidated = 1; s->invalidated = 1;
} else { } else {
printf("%s: Bad width: %i\n", __func__, value); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad width: %i\n", __func__, value);
} }
break; break;
@ -1011,13 +1014,15 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
s->new_height = value; s->new_height = value;
s->invalidated = 1; s->invalidated = 1;
} else { } else {
printf("%s: Bad height: %i\n", __func__, value); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad height: %i\n", __func__, value);
} }
break; break;
case SVGA_REG_BITS_PER_PIXEL: case SVGA_REG_BITS_PER_PIXEL:
if (value != 32) { if (value != 32) {
printf("%s: Bad bits per pixel: %i bits\n", __func__, value); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad bits per pixel: %i bits\n", __func__, value);
s->config = 0; s->config = 0;
s->invalidated = 1; s->invalidated = 1;
} }
@ -1082,7 +1087,8 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
s->scratch[s->index - SVGA_SCRATCH_BASE] = value; s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
break; break;
} }
printf("%s: Bad register %02x\n", __func__, s->index); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad register %02x\n", __func__, s->index);
} }
} }
@ -1300,7 +1306,7 @@ static void pci_vmsvga_realize(PCIDevice *dev, Error **errp)
dev->config[PCI_LATENCY_TIMER] = 0x40; dev->config[PCI_LATENCY_TIMER] = 0x40;
dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */ dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */
memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip, memory_region_init_io(&s->io_bar, OBJECT(dev), &vmsvga_io_ops, &s->chip,
"vmsvga-io", 0x10); "vmsvga-io", 0x10);
memory_region_set_flush_coalesced(&s->io_bar); memory_region_set_flush_coalesced(&s->io_bar);
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);

10
hw/display/xlnx_dp.c
View File

@ -1,5 +1,5 @@
/* /*
* xlnx_dp.c * Xilinx Display Port
* *
* Copyright (C) 2015 : GreenSocs Ltd * Copyright (C) 2015 : GreenSocs Ltd
* http://www.greensocs.com/ , email: info@greensocs.com * http://www.greensocs.com/ , email: info@greensocs.com
@ -24,6 +24,7 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/log.h" #include "qemu/log.h"
#include "qemu/module.h" #include "qemu/module.h"
#include "hw/display/xlnx_dp.h" #include "hw/display/xlnx_dp.h"
@ -465,7 +466,7 @@ static uint8_t xlnx_dp_aux_pop_tx_fifo(XlnxDPState *s)
uint8_t ret; uint8_t ret;
if (fifo8_is_empty(&s->tx_fifo)) { if (fifo8_is_empty(&s->tx_fifo)) {
DPRINTF("tx_fifo underflow..\n"); error_report("%s: TX_FIFO underflow", __func__);
abort(); abort();
} }
ret = fifo8_pop(&s->tx_fifo); ret = fifo8_pop(&s->tx_fifo);
@ -525,6 +526,7 @@ static void xlnx_dp_aux_set_command(XlnxDPState *s, uint32_t value)
qemu_log_mask(LOG_UNIMP, "xlnx_dp: Write i2c status not implemented\n"); qemu_log_mask(LOG_UNIMP, "xlnx_dp: Write i2c status not implemented\n");
break; break;
default: default:
error_report("%s: invalid command: %u", __func__, cmd);
abort(); abort();
} }
@ -631,7 +633,7 @@ static void xlnx_dp_change_graphic_fmt(XlnxDPState *s)
s->g_plane.format = PIXMAN_b8g8r8; s->g_plane.format = PIXMAN_b8g8r8;
break; break;
default: default:
DPRINTF("error: unsupported graphic format %u.\n", error_report("%s: unsupported graphic format %u", __func__,
s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK); s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK);
abort(); abort();
} }
@ -647,7 +649,7 @@ static void xlnx_dp_change_graphic_fmt(XlnxDPState *s)
s->v_plane.format = PIXMAN_x8b8g8r8; s->v_plane.format = PIXMAN_x8b8g8r8;
break; break;
default: default:
DPRINTF("error: unsupported video format %u.\n", error_report("%s: unsupported video format %u", __func__,
s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK); s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK);
abort(); abort();
} }

1
include/hw/display/edid.h
View File

@ -2,6 +2,7 @@
#define EDID_H #define EDID_H
#include "qom/object.h" #include "qom/object.h"
#include "hw/qdev-properties.h"
typedef struct qemu_edid_info { typedef struct qemu_edid_info {
const char *vendor; /* http://www.uefi.org/pnp_id_list */ const char *vendor; /* http://www.uefi.org/pnp_id_list */