ide: split away ide-macio.c
create ide-macio.c and place macio support there. only build ide-macio support for platforms using it. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Gerd Hoffmann
Anthony Liguori
parent
977e1244e8
commit
b884220990
355
hw/ide-macio.c
Normal file
355
hw/ide-macio.c
Normal file
@ -0,0 +1,355 @@
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/*
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* QEMU IDE Emulation: MacIO support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "block.h"
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#include "block_int.h"
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#include "sysemu.h"
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#include "dma.h"
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#include "ppc_mac.h"
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#include "mac_dbdma.h"
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#include "ide-internal.h"
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/***********************************************************/
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/* MacIO based PowerPC IDE */
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typedef struct MACIOIDEState {
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IDEBus bus;
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BlockDriverAIOCB *aiocb;
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} MACIOIDEState;
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static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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if (ret < 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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ide_atapi_io_error(s, ret);
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io->dma_end(opaque);
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return;
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}
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if (s->io_buffer_size > 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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s->packet_transfer_size -= s->io_buffer_size;
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s->io_buffer_index += s->io_buffer_size;
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s->lba += s->io_buffer_index >> 11;
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s->io_buffer_index &= 0x7ff;
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}
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if (s->packet_transfer_size <= 0)
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ide_atapi_cmd_ok(s);
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if (io->len == 0) {
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io->dma_end(opaque);
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return;
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}
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/* launch next transfer */
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s->io_buffer_size = io->len;
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qemu_sglist_init(&s->sg, io->len / TARGET_PAGE_SIZE + 1);
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qemu_sglist_add(&s->sg, io->addr, io->len);
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io->addr += io->len;
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io->len = 0;
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m->aiocb = dma_bdrv_read(s->bs, &s->sg,
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(int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
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pmac_ide_atapi_transfer_cb, io);
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if (!m->aiocb) {
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qemu_sglist_destroy(&s->sg);
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/* Note: media not present is the most likely case */
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ide_atapi_cmd_error(s, SENSE_NOT_READY,
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ASC_MEDIUM_NOT_PRESENT);
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io->dma_end(opaque);
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return;
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}
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}
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static void pmac_ide_transfer_cb(void *opaque, int ret)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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int n;
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int64_t sector_num;
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if (ret < 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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ide_dma_error(s);
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io->dma_end(io);
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return;
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}
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sector_num = ide_get_sector(s);
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if (s->io_buffer_size > 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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n = (s->io_buffer_size + 0x1ff) >> 9;
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sector_num += n;
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ide_set_sector(s, sector_num);
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s->nsector -= n;
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}
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/* end of transfer ? */
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if (s->nsector == 0) {
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s->status = READY_STAT | SEEK_STAT;
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ide_set_irq(s);
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}
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/* end of DMA ? */
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if (io->len == 0) {
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io->dma_end(io);
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return;
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}
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/* launch next transfer */
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s->io_buffer_index = 0;
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s->io_buffer_size = io->len;
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qemu_sglist_init(&s->sg, io->len / TARGET_PAGE_SIZE + 1);
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qemu_sglist_add(&s->sg, io->addr, io->len);
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io->addr += io->len;
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io->len = 0;
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if (s->is_read)
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m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
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pmac_ide_transfer_cb, io);
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else
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m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
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pmac_ide_transfer_cb, io);
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if (!m->aiocb)
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pmac_ide_transfer_cb(io, -1);
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}
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static void pmac_ide_transfer(DBDMA_io *io)
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{
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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s->io_buffer_size = 0;
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if (s->is_cdrom) {
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pmac_ide_atapi_transfer_cb(io, 0);
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return;
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}
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pmac_ide_transfer_cb(io, 0);
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}
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static void pmac_ide_flush(DBDMA_io *io)
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{
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MACIOIDEState *m = io->opaque;
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if (m->aiocb)
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qemu_aio_flush();
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}
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/* PowerMac IDE memory IO */
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static void pmac_ide_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t val)
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{
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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switch (addr) {
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case 1 ... 7:
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ide_ioport_write(&d->bus, addr, val);
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break;
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case 8:
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case 22:
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ide_cmd_write(&d->bus, 0, val);
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break;
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default:
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break;
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}
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}
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static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
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{
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uint8_t retval;
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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switch (addr) {
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case 1 ... 7:
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retval = ide_ioport_read(&d->bus, addr);
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break;
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case 8:
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case 22:
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retval = ide_status_read(&d->bus, 0);
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break;
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default:
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retval = 0xFF;
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break;
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}
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return retval;
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}
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static void pmac_ide_writew (void *opaque,
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target_phys_addr_t addr, uint32_t val)
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{
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap16(val);
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#endif
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if (addr == 0) {
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ide_data_writew(&d->bus, 0, val);
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}
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}
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static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
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{
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uint16_t retval;
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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if (addr == 0) {
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retval = ide_data_readw(&d->bus, 0);
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} else {
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retval = 0xFFFF;
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}
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#ifdef TARGET_WORDS_BIGENDIAN
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retval = bswap16(retval);
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#endif
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return retval;
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}
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static void pmac_ide_writel (void *opaque,
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target_phys_addr_t addr, uint32_t val)
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{
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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if (addr == 0) {
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ide_data_writel(&d->bus, 0, val);
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}
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}
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static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
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{
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uint32_t retval;
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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if (addr == 0) {
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retval = ide_data_readl(&d->bus, 0);
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} else {
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retval = 0xFFFFFFFF;
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}
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#ifdef TARGET_WORDS_BIGENDIAN
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retval = bswap32(retval);
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#endif
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return retval;
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}
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static CPUWriteMemoryFunc *pmac_ide_write[] = {
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pmac_ide_writeb,
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pmac_ide_writew,
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pmac_ide_writel,
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};
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static CPUReadMemoryFunc *pmac_ide_read[] = {
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pmac_ide_readb,
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pmac_ide_readw,
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pmac_ide_readl,
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};
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static void pmac_ide_save(QEMUFile *f, void *opaque)
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{
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MACIOIDEState *d = opaque;
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unsigned int i;
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/* per IDE interface data */
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idebus_save(f, &d->bus);
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/* per IDE drive data */
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for(i = 0; i < 2; i++) {
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ide_save(f, &d->bus.ifs[i]);
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}
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}
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static int pmac_ide_load(QEMUFile *f, void *opaque, int version_id)
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{
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MACIOIDEState *d = opaque;
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unsigned int i;
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if (version_id != 1 && version_id != 3)
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return -EINVAL;
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/* per IDE interface data */
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idebus_load(f, &d->bus, version_id);
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/* per IDE drive data */
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for(i = 0; i < 2; i++) {
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ide_load(f, &d->bus.ifs[i], version_id);
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}
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return 0;
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}
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static void pmac_ide_reset(void *opaque)
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{
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MACIOIDEState *d = opaque;
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ide_reset(d->bus.ifs +0);
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ide_reset(d->bus.ifs +1);
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}
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/* hd_table must contain 4 block drivers */
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/* PowerMac uses memory mapped registers, not I/O. Return the memory
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I/O index to access the ide. */
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int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
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void *dbdma, int channel, qemu_irq dma_irq)
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{
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MACIOIDEState *d;
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int pmac_ide_memory;
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d = qemu_mallocz(sizeof(MACIOIDEState));
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ide_init2(&d->bus, hd_table[0], hd_table[1], irq);
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if (dbdma)
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DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
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pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
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pmac_ide_write, d);
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register_savevm("ide", 0, 3, pmac_ide_save, pmac_ide_load, d);
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qemu_register_reset(pmac_ide_reset, d);
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pmac_ide_reset(d);
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return pmac_ide_memory;
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}
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327
hw/ide.c
327
hw/ide.c
@ -31,8 +31,6 @@
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#include "block_int.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "ppc_mac.h"
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#include "mac_dbdma.h"
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#include "sh.h"
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#include "dma.h"
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#include "ide-internal.h"
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@ -2701,331 +2699,6 @@ void ide_dma_cancel(BMDMAState *bm)
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}
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}
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#if defined(TARGET_PPC)
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/***********************************************************/
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/* MacIO based PowerPC IDE */
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typedef struct MACIOIDEState {
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IDEBus bus;
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BlockDriverAIOCB *aiocb;
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} MACIOIDEState;
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static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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if (ret < 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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ide_atapi_io_error(s, ret);
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io->dma_end(opaque);
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return;
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}
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if (s->io_buffer_size > 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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s->packet_transfer_size -= s->io_buffer_size;
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s->io_buffer_index += s->io_buffer_size;
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s->lba += s->io_buffer_index >> 11;
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s->io_buffer_index &= 0x7ff;
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}
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if (s->packet_transfer_size <= 0)
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ide_atapi_cmd_ok(s);
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if (io->len == 0) {
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io->dma_end(opaque);
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return;
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}
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/* launch next transfer */
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s->io_buffer_size = io->len;
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qemu_sglist_init(&s->sg, io->len / TARGET_PAGE_SIZE + 1);
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qemu_sglist_add(&s->sg, io->addr, io->len);
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io->addr += io->len;
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io->len = 0;
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m->aiocb = dma_bdrv_read(s->bs, &s->sg,
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(int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
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pmac_ide_atapi_transfer_cb, io);
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if (!m->aiocb) {
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qemu_sglist_destroy(&s->sg);
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/* Note: media not present is the most likely case */
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ide_atapi_cmd_error(s, SENSE_NOT_READY,
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ASC_MEDIUM_NOT_PRESENT);
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io->dma_end(opaque);
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return;
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}
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}
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static void pmac_ide_transfer_cb(void *opaque, int ret)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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int n;
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int64_t sector_num;
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if (ret < 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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ide_dma_error(s);
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io->dma_end(io);
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return;
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}
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sector_num = ide_get_sector(s);
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if (s->io_buffer_size > 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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n = (s->io_buffer_size + 0x1ff) >> 9;
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sector_num += n;
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ide_set_sector(s, sector_num);
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s->nsector -= n;
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}
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/* end of transfer ? */
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if (s->nsector == 0) {
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s->status = READY_STAT | SEEK_STAT;
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ide_set_irq(s);
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}
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/* end of DMA ? */
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if (io->len == 0) {
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io->dma_end(io);
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return;
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}
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/* launch next transfer */
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s->io_buffer_index = 0;
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s->io_buffer_size = io->len;
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qemu_sglist_init(&s->sg, io->len / TARGET_PAGE_SIZE + 1);
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qemu_sglist_add(&s->sg, io->addr, io->len);
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io->addr += io->len;
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io->len = 0;
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if (s->is_read)
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m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
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pmac_ide_transfer_cb, io);
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else
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m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
|
||||
pmac_ide_transfer_cb, io);
|
||||
if (!m->aiocb)
|
||||
pmac_ide_transfer_cb(io, -1);
|
||||
}
|
||||
|
||||
static void pmac_ide_transfer(DBDMA_io *io)
|
||||
{
|
||||
MACIOIDEState *m = io->opaque;
|
||||
IDEState *s = idebus_active_if(&m->bus);
|
||||
|
||||
s->io_buffer_size = 0;
|
||||
if (s->is_cdrom) {
|
||||
pmac_ide_atapi_transfer_cb(io, 0);
|
||||
return;
|
||||
}
|
||||
|
||||
pmac_ide_transfer_cb(io, 0);
|
||||
}
|
||||
|
||||
static void pmac_ide_flush(DBDMA_io *io)
|
||||
{
|
||||
MACIOIDEState *m = io->opaque;
|
||||
|
||||
if (m->aiocb)
|
||||
qemu_aio_flush();
|
||||
}
|
||||
|
||||
/* PowerMac IDE memory IO */
|
||||
static void pmac_ide_writeb (void *opaque,
|
||||
target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
MACIOIDEState *d = opaque;
|
||||
|
||||
addr = (addr & 0xFFF) >> 4;
|
||||
switch (addr) {
|
||||
case 1 ... 7:
|
||||
ide_ioport_write(&d->bus, addr, val);
|
||||
break;
|
||||
case 8:
|
||||
case 22:
|
||||
ide_cmd_write(&d->bus, 0, val);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
|
||||
{
|
||||
uint8_t retval;
|
||||
MACIOIDEState *d = opaque;
|
||||
|
||||
addr = (addr & 0xFFF) >> 4;
|
||||
switch (addr) {
|
||||
case 1 ... 7:
|
||||
retval = ide_ioport_read(&d->bus, addr);
|
||||
break;
|
||||
case 8:
|
||||
case 22:
|
||||
retval = ide_status_read(&d->bus, 0);
|
||||
break;
|
||||
default:
|
||||
retval = 0xFF;
|
||||
break;
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
static void pmac_ide_writew (void *opaque,
|
||||
target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
MACIOIDEState *d = opaque;
|
||||
|
||||
addr = (addr & 0xFFF) >> 4;
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
val = bswap16(val);
|
||||
#endif
|
||||
if (addr == 0) {
|
||||
ide_data_writew(&d->bus, 0, val);
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
|
||||
{
|
||||
uint16_t retval;
|
||||
MACIOIDEState *d = opaque;
|
||||
|
||||
addr = (addr & 0xFFF) >> 4;
|
||||
if (addr == 0) {
|
||||
retval = ide_data_readw(&d->bus, 0);
|
||||
} else {
|
||||
retval = 0xFFFF;
|
||||
}
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
retval = bswap16(retval);
|
||||
#endif
|
||||
return retval;
|
||||
}
|
||||
|
||||
static void pmac_ide_writel (void *opaque,
|
||||
target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
MACIOIDEState *d = opaque;
|
||||
|
||||
addr = (addr & 0xFFF) >> 4;
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
val = bswap32(val);
|
||||
#endif
|
||||
if (addr == 0) {
|
||||
ide_data_writel(&d->bus, 0, val);
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
|
||||
{
|
||||
uint32_t retval;
|
||||
MACIOIDEState *d = opaque;
|
||||
|
||||
addr = (addr & 0xFFF) >> 4;
|
||||
if (addr == 0) {
|
||||
retval = ide_data_readl(&d->bus, 0);
|
||||
} else {
|
||||
retval = 0xFFFFFFFF;
|
||||
}
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
retval = bswap32(retval);
|
||||
#endif
|
||||
return retval;
|
||||
}
|
||||
|
||||
static CPUWriteMemoryFunc * const pmac_ide_write[] = {
|
||||
pmac_ide_writeb,
|
||||
pmac_ide_writew,
|
||||
pmac_ide_writel,
|
||||
};
|
||||
|
||||
static CPUReadMemoryFunc * const pmac_ide_read[] = {
|
||||
pmac_ide_readb,
|
||||
pmac_ide_readw,
|
||||
pmac_ide_readl,
|
||||
};
|
||||
|
||||
static void pmac_ide_save(QEMUFile *f, void *opaque)
|
||||
{
|
||||
MACIOIDEState *d = opaque;
|
||||
unsigned int i;
|
||||
|
||||
/* per IDE interface data */
|
||||
idebus_save(f, &d->bus);
|
||||
|
||||
/* per IDE drive data */
|
||||
for(i = 0; i < 2; i++) {
|
||||
ide_save(f, &d->bus.ifs[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static int pmac_ide_load(QEMUFile *f, void *opaque, int version_id)
|
||||
{
|
||||
MACIOIDEState *d = opaque;
|
||||
unsigned int i;
|
||||
|
||||
if (version_id != 1 && version_id != 3)
|
||||
return -EINVAL;
|
||||
|
||||
/* per IDE interface data */
|
||||
idebus_load(f, &d->bus, version_id);
|
||||
|
||||
/* per IDE drive data */
|
||||
for(i = 0; i < 2; i++) {
|
||||
ide_load(f, &d->bus.ifs[i], version_id);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pmac_ide_reset(void *opaque)
|
||||
{
|
||||
MACIOIDEState *d = opaque;
|
||||
|
||||
ide_reset(d->bus.ifs +0);
|
||||
ide_reset(d->bus.ifs +1);
|
||||
}
|
||||
|
||||
/* hd_table must contain 4 block drivers */
|
||||
/* PowerMac uses memory mapped registers, not I/O. Return the memory
|
||||
I/O index to access the ide. */
|
||||
int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
|
||||
void *dbdma, int channel, qemu_irq dma_irq)
|
||||
{
|
||||
MACIOIDEState *d;
|
||||
int pmac_ide_memory;
|
||||
|
||||
d = qemu_mallocz(sizeof(MACIOIDEState));
|
||||
ide_init2(&d->bus, hd_table[0], hd_table[1], irq);
|
||||
|
||||
if (dbdma)
|
||||
DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
|
||||
|
||||
pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
|
||||
pmac_ide_write, d);
|
||||
register_savevm("ide", 0, 3, pmac_ide_save, pmac_ide_load, d);
|
||||
qemu_register_reset(pmac_ide_reset, d);
|
||||
pmac_ide_reset(d);
|
||||
|
||||
return pmac_ide_memory;
|
||||
}
|
||||
#endif /* TARGET_PPC */
|
||||
|
||||
/***********************************************************/
|
||||
/* MMIO based ide port
|
||||
* This emulates IDE device connected directly to the CPU bus without
|
||||
|
||||
4
hw/ide.h
4
hw/ide.h
@ -15,4 +15,8 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
|
||||
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
|
||||
qemu_irq *pic);
|
||||
|
||||
/* ide-macio.c */
|
||||
int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
|
||||
void *dbdma, int channel, qemu_irq dma_irq);
|
||||
|
||||
#endif /* HW_IDE_H */
|
||||
|
||||
@ -49,10 +49,6 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
|
||||
int dbdma_mem_index, int cuda_mem_index, void *nvram,
|
||||
int nb_ide, int *ide_mem_index, int escc_mem_index);
|
||||
|
||||
/* NewWorld PowerMac IDE */
|
||||
int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
|
||||
void *dbdma, int channel, qemu_irq dma_irq);
|
||||
|
||||
/* Heathrow PIC */
|
||||
qemu_irq *heathrow_pic_init(int *pmem_index,
|
||||
int nb_cpus, qemu_irq **irqs);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user