mirror of https://gitlab.com/qemu-project/qemu
docs: updates on the POWER9 XIVE interrupt controller documentation
This includes various small updates and a better description of the chosen interrupt mode resulting from the combination of the 'ic-mode' machine option, the 'kernel_irqchip' option, guest support and KVM support. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190612160425.27670-1-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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Cédric Le Goater
David Gibson
parent
fad189d1f6
commit
b87a0100cd
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@ -34,19 +34,118 @@ CAS Negotiation
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---------------
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QEMU advertises the supported interrupt modes in the device tree
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property "ibm,arch-vec-5-platform-support" in byte 23 and the OS
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Selection for XIVE is indicated in the "ibm,architecture-vec-5"
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property ``ibm,arch-vec-5-platform-support`` in byte 23 and the OS
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Selection for XIVE is indicated in the ``ibm,architecture-vec-5``
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property byte 23.
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The interrupt modes supported by the machine depend on the CPU type
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(POWER9 is required for XIVE) but also on the machine property
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``ic-mode`` which can be set on the command line. It can take the
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following values: ``xics``, ``xive``, ``dual`` and currently ``xics``
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is the default but it may change in the future.
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following values: ``xics``, ``xive``, and ``dual`` which is the
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default mode. ``dual`` means that both modes XICS **and** XIVE are
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supported and if the guest OS supports XIVE, this mode will be
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selected.
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The choosen interrupt mode is activated after a reconfiguration done
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in a machine reset.
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KVM negotiation
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---------------
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When the guest starts under KVM, the capabilities of the host kernel
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and QEMU are also negotiated. Depending on the version of the host
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kernel, KVM will advertise the XIVE capability to QEMU or not.
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Nevertheless, the available interrupt modes in the machine should not
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depend on the XIVE KVM capability of the host. On older kernels
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without XIVE KVM support, QEMU will use the emulated XIVE device as a
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fallback and on newer kernels (>=5.2), the KVM XIVE device.
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As a final refinement, the user can also switch the use of the KVM
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device with the machine option ``kernel_irqchip``.
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XIVE support in KVM
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~~~~~~~~~~~~~~~~~~~
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For guest OSes supporting XIVE, the resulting interrupt modes on host
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kernels with XIVE KVM support are the following:
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============== ============= ============= ================
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ic-mode kernel_irqchip
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-------------- ----------------------------------------------
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/ allowed off on
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(default)
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============== ============= ============= ================
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dual (default) XIVE KVM XIVE emul. XIVE KVM
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xive XIVE KVM XIVE emul. XIVE KVM
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xics XICS KVM XICS emul. XICS KVM
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============== ============= ============= ================
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For legacy guest OSes without XIVE support, the resulting interrupt
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modes are the following:
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============== ============= ============= ================
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ic-mode kernel_irqchip
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-------------- ----------------------------------------------
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/ allowed off on
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(default)
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============== ============= ============= ================
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dual (default) XICS KVM XICS emul. XICS KVM
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xive QEMU error(3) QEMU error(3) QEMU error(3)
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xics XICS KVM XICS emul. XICS KVM
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============== ============= ============= ================
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(3) QEMU fails at CAS with ``Guest requested unavailable interrupt
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mode (XICS), either don't set the ic-mode machine property or try
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ic-mode=xics or ic-mode=dual``
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No XIVE support in KVM
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~~~~~~~~~~~~~~~~~~~~~~
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For guest OSes supporting XIVE, the resulting interrupt modes on host
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kernels without XIVE KVM support are the following:
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============== ============= ============= ================
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ic-mode kernel_irqchip
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-------------- ----------------------------------------------
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/ allowed off on
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(default)
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============== ============= ============= ================
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dual (default) XIVE emul.(1) XIVE emul. QEMU error (2)
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xive XIVE emul.(1) XIVE emul. QEMU error (2)
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xics XICS KVM XICS emul. XICS KVM
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============== ============= ============= ================
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(1) QEMU warns with ``warning: kernel_irqchip requested but unavailable:
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IRQ_XIVE capability must be present for KVM``
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(2) QEMU fails with ``kernel_irqchip requested but unavailable:
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IRQ_XIVE capability must be present for KVM``
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For legacy guest OSes without XIVE support, the resulting interrupt
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modes are the following:
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============== ============= ============= ================
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ic-mode kernel_irqchip
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-------------- ----------------------------------------------
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/ allowed off on
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(default)
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============== ============= ============= ================
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dual (default) QEMU error(4) XICS emul. QEMU error(4)
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xive QEMU error(3) QEMU error(3) QEMU error(3)
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xics XICS KVM XICS emul. XICS KVM
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============== ============= ============= ================
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(3) QEMU fails at CAS with ``Guest requested unavailable interrupt
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mode (XICS), either don't set the ic-mode machine property or try
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ic-mode=xics or ic-mode=dual``
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(4) QEMU/KVM incompatibility due to device destruction in reset. This
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needs to be addressed more cleanly with an error.
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XIVE Device tree properties
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---------------------------
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@ -92,10 +191,11 @@ for both interrupt mode. The different ranges are defined as follow :
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- ``0x0000 .. 0x0FFF`` 4K CPU IPIs (only used under XIVE)
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- ``0x1000 .. 0x1000`` 1 EPOW
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- ``0x1001 .. 0x1001`` 1 HOTPLUG
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- ``0x1002 .. 0x10FF`` unused
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- ``0x1100 .. 0x11FF`` 256 VIO devices
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- ``0x1200 .. 0x127F`` 32 PHBs devices
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- ``0x1200 .. 0x127F`` 32x4 LSIs for PHB devices
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- ``0x1280 .. 0x12FF`` unused
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- ``0x1300 .. 0x1FFF`` PHB MSIs
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- ``0x1300 .. 0x1FFF`` PHB MSIs (dynamically allocated)
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Monitoring XIVE
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---------------
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@ -20,10 +20,11 @@ The XIVE IC is composed of three sub-engines, each taking care of a
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processing layer of external interrupts:
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- Interrupt Virtualization Source Engine (IVSE), or Source Controller
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(SC). These are found in PCI PHBs, in the PSI host bridge
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controller, but also inside the main controller for the core IPIs
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and other sub-chips (NX, CAP, NPU) of the chip/processor. They are
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configured to feed the IVRE with events.
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(SC). These are found in PCI PHBs, in the Processor Service
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Interface (PSI) host bridge Controller, but also inside the main
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controller for the core IPIs and other sub-chips (NX, CAP, NPU) of
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the chip/processor. They are configured to feed the IVRE with
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events.
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- Interrupt Virtualization Routing Engine (IVRE) or Virtualization
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Controller (VC). It handles event coalescing and perform interrupt
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routing by matching an event source number with an Event
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