PPC: Add e5500 CPU target
This patch adds e5500's CPU initialization to the TCG CPU initialization code. Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf
parent
e9cd84b90b
commit
b81ccf8ae7
@ -4424,16 +4424,69 @@ static void init_proc_e300 (CPUPPCState *env)
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#define check_pow_e500mc check_pow_none
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#define init_proc_e500mc init_proc_e500mc
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/* e5500 core */
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#define POWERPC_INSNS_e5500 (PPC_INSNS_BASE | PPC_ISEL | \
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PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
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PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
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PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
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PPC_FLOAT | PPC_FLOAT_FRES | \
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PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
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PPC_FLOAT_STFIWX | PPC_WAIT | \
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PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | \
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PPC_64B | PPC_POPCNTB | PPC_POPCNTWD)
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#define POWERPC_INSNS2_e5500 (PPC2_BOOKE206 | PPC2_PRCNTL)
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#define POWERPC_MSRM_e5500 (0x000000009402FB36ULL)
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#define POWERPC_MMU_e5500 (POWERPC_MMU_BOOKE206)
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#define POWERPC_EXCP_e5500 (POWERPC_EXCP_BOOKE)
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#define POWERPC_INPUT_e5500 (PPC_FLAGS_INPUT_BookE)
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/* Fixme: figure out the correct flag for e5500 */
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#define POWERPC_BFDM_e5500 (bfd_mach_ppc_e500)
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#define POWERPC_FLAG_e5500 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
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POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
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#define check_pow_e5500 check_pow_none
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#define init_proc_e5500 init_proc_e5500
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#if !defined(CONFIG_USER_ONLY)
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static void spr_write_mas73(void *opaque, int sprn, int gprn)
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{
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TCGv val = tcg_temp_new();
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tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
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gen_store_spr(SPR_BOOKE_MAS3, val);
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tcg_gen_shri_tl(val, gprn, 32);
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gen_store_spr(SPR_BOOKE_MAS7, val);
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tcg_temp_free(val);
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}
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static void spr_read_mas73(void *opaque, int gprn, int sprn)
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{
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TCGv mas7 = tcg_temp_new();
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TCGv mas3 = tcg_temp_new();
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gen_load_spr(mas7, SPR_BOOKE_MAS7);
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tcg_gen_shli_tl(mas7, mas7, 32);
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gen_load_spr(mas3, SPR_BOOKE_MAS3);
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tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
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tcg_temp_free(mas3);
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tcg_temp_free(mas7);
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}
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static void spr_load_epr(void *opaque, int gprn, int sprn)
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{
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gen_helper_load_epr(cpu_gpr[gprn], cpu_env);
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}
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#endif
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enum fsl_e500_version {
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fsl_e500v1,
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fsl_e500v2,
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fsl_e500mc,
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fsl_e5500,
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};
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static void init_proc_e500 (CPUPPCState *env, int version)
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{
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uint32_t tlbncfg[2];
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uint64_t ivor_mask = 0x0000000F0000FFFFULL;
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uint64_t ivor_mask;
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uint64_t ivpr_mask = 0xFFFF0000ULL;
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uint32_t l1cfg0 = 0x3800 /* 8 ways */
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| 0x0020; /* 32 kb */
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@ -4448,8 +4501,16 @@ static void init_proc_e500 (CPUPPCState *env, int version)
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* complain when accessing them.
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* gen_spr_BookE(env, 0x0000000F0000FD7FULL);
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*/
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if (version == fsl_e500mc) {
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ivor_mask = 0x000003FE0000FFFFULL;
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switch (version) {
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case fsl_e500v1:
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case fsl_e500v2:
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default:
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ivor_mask = 0x0000000F0000FFFFULL;
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break;
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case fsl_e500mc:
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case fsl_e5500:
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ivor_mask = 0x000003FE0000FFFFULL;
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break;
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}
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gen_spr_BookE(env, ivor_mask);
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/* Processor identification */
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@ -4477,6 +4538,7 @@ static void init_proc_e500 (CPUPPCState *env, int version)
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tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
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break;
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case fsl_e500mc:
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case fsl_e5500:
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tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
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tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
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break;
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@ -4492,6 +4554,7 @@ static void init_proc_e500 (CPUPPCState *env, int version)
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env->icache_line_size = 32;
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break;
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case fsl_e500mc:
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case fsl_e5500:
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env->dcache_line_size = 64;
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env->icache_line_size = 64;
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l1cfg0 |= 0x1000000; /* 64 byte cache block size */
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@ -4567,6 +4630,22 @@ static void init_proc_e500 (CPUPPCState *env, int version)
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_booke206_mmucsr0,
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0x00000000);
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spr_register(env, SPR_BOOKE_EPR, "EPR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_load_epr, SPR_NOACCESS,
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0x00000000);
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/* XXX better abstract into Emb.xxx features */
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if (version == fsl_e5500) {
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spr_register(env, SPR_BOOKE_EPCR, "EPCR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_mas73, &spr_write_mas73,
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0x00000000);
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ivpr_mask = (target_ulong)~0xFFFFULL;
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}
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 0;
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@ -4596,6 +4675,13 @@ static void init_proc_e500mc(CPUPPCState *env)
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init_proc_e500(env, fsl_e500mc);
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}
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#ifdef TARGET_PPC64
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static void init_proc_e5500(CPUPPCState *env)
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{
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init_proc_e500(env, fsl_e5500);
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}
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#endif
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/* Non-embedded PowerPC */
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/* POWER : same as 601, without mfmsr, mfsr */
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@ -7134,6 +7220,7 @@ enum {
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CPU_POWERPC_e500v2_v22 = 0x80210022,
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CPU_POWERPC_e500v2_v30 = 0x80210030,
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CPU_POWERPC_e500mc = 0x80230020,
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CPU_POWERPC_e5500 = 0x80240020,
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/* MPC85xx microcontrollers */
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#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
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#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
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@ -8528,6 +8615,9 @@ static const ppc_def_t ppc_defs[] = {
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/* PowerPC e500v2 v3.0 core */
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POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
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POWERPC_DEF("e500mc", CPU_POWERPC_e500mc, e500mc),
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#ifdef TARGET_PPC64
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POWERPC_DEF("e5500", CPU_POWERPC_e5500, e5500),
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#endif
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/* PowerPC e500 microcontrollers */
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/* MPC8533 */
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POWERPC_DEF_SVR("MPC8533",
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