target/i386: allow modifying TCG phys-addr-bits
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -6785,21 +6785,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
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cpu->phys_bits = cpu->host_phys_bits_limit;
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cpu->phys_bits = cpu->host_phys_bits_limit;
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}
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}
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}
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}
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}
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if (cpu->phys_bits &&
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if (cpu->phys_bits &&
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(cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
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(cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
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cpu->phys_bits < 32)) {
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cpu->phys_bits < 32)) {
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error_setg(errp, "phys-bits should be between 32 and %u "
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error_setg(errp, "phys-bits should be between 32 and %u "
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" (but is %u)",
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" (but is %u)",
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TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
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TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
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return;
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return;
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}
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} else {
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if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
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error_setg(errp, "TCG only supports phys-bits=%u",
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TCG_PHYS_ADDR_BITS);
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return;
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}
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}
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}
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/* 0 means it was not explicitly set by the user (or by machine
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/* 0 means it was not explicitly set by the user (or by machine
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* compat_props or by the host code above). In this case, the default
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* compat_props or by the host code above). In this case, the default
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@ -290,7 +290,6 @@ typedef enum X86Seg {
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#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
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#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
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#define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
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#define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
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#define PG_ADDRESS_MASK 0x000ffffffffff000LL
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#define PG_ADDRESS_MASK 0x000ffffffffff000LL
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#define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
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#define PG_HI_USER_MASK 0x7ff0000000000000LL
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#define PG_HI_USER_MASK 0x7ff0000000000000LL
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#define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
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#define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
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#define PG_NX_MASK (1ULL << PG_NX_BIT)
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#define PG_NX_MASK (1ULL << PG_NX_BIT)
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@ -142,8 +142,9 @@ void raise_exception_ra(CPUX86State *env, int exception_index, uintptr_t retaddr
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static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
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static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
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int *prot)
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int *prot)
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{
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{
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CPUX86State *env = &X86_CPU(cs)->env;
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X86CPU *cpu = X86_CPU(cs);
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uint64_t rsvd_mask = PG_HI_RSVD_MASK;
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CPUX86State *env = &cpu->env;
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uint64_t rsvd_mask = PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys_bits);
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uint64_t ptep, pte;
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uint64_t ptep, pte;
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uint64_t exit_info_1 = 0;
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uint64_t exit_info_1 = 0;
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target_ulong pde_addr, pte_addr;
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target_ulong pde_addr, pte_addr;
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@ -358,7 +359,7 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, int size,
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int error_code = 0;
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int error_code = 0;
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int is_dirty, prot, page_size, is_write, is_user;
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int is_dirty, prot, page_size, is_write, is_user;
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hwaddr paddr;
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hwaddr paddr;
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uint64_t rsvd_mask = PG_HI_RSVD_MASK;
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uint64_t rsvd_mask = PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys_bits);
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uint32_t page_offset;
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uint32_t page_offset;
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target_ulong vaddr;
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target_ulong vaddr;
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uint32_t pkr;
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uint32_t pkr;
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@ -25,17 +25,13 @@
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/* Maximum instruction code size */
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/* Maximum instruction code size */
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#define TARGET_MAX_INSN_SIZE 16
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#define TARGET_MAX_INSN_SIZE 16
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/*
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#if defined(TARGET_X86_64)
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* XXX: This value should match the one returned by CPUID
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* and in exec.c
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*/
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# if defined(TARGET_X86_64)
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# define TCG_PHYS_ADDR_BITS 40
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# define TCG_PHYS_ADDR_BITS 40
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# else
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#else
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# define TCG_PHYS_ADDR_BITS 36
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# define TCG_PHYS_ADDR_BITS 36
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# endif
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#endif
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#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
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QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS);
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/**
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/**
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* x86_cpu_do_interrupt:
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* x86_cpu_do_interrupt:
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