s390x/ioinst: Rework memory access in TSCH instruction
Change the TSCH handler to use the new logical memory access functions. Since the channel should not be updated in case of a protection or access exception while writing to the guest memory, the css_do_tsch() has to be split up into two parts, one for retrieving the IRB and one for the update. Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
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@ -801,7 +801,8 @@ out:
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return ret;
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}
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static void copy_irb_to_guest(IRB *dest, const IRB *src, PMCW *pmcw)
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static void copy_irb_to_guest(IRB *dest, const IRB *src, PMCW *pmcw,
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int *irb_len)
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{
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int i;
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uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL;
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@ -815,6 +816,8 @@ static void copy_irb_to_guest(IRB *dest, const IRB *src, PMCW *pmcw)
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for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) {
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dest->ecw[i] = cpu_to_be32(src->ecw[i]);
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}
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*irb_len = sizeof(*dest) - sizeof(dest->emw);
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/* extended measurements enabled? */
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if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) ||
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!(pmcw->flags & PMCW_FLAGS_MASK_TF) ||
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@ -832,26 +835,21 @@ static void copy_irb_to_guest(IRB *dest, const IRB *src, PMCW *pmcw)
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dest->emw[i] = cpu_to_be32(src->emw[i]);
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}
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}
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*irb_len = sizeof(*dest);
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}
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int css_do_tsch(SubchDev *sch, IRB *target_irb)
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int css_do_tsch_get_irb(SubchDev *sch, IRB *target_irb, int *irb_len)
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{
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SCSW *s = &sch->curr_status.scsw;
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PMCW *p = &sch->curr_status.pmcw;
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uint16_t stctl;
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uint16_t fctl;
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uint16_t actl;
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IRB irb;
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int ret;
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if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) {
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ret = 3;
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goto out;
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return 3;
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}
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stctl = s->ctrl & SCSW_CTRL_MASK_STCTL;
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fctl = s->ctrl & SCSW_CTRL_MASK_FCTL;
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actl = s->ctrl & SCSW_CTRL_MASK_ACTL;
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/* Prepare the irb for the guest. */
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memset(&irb, 0, sizeof(IRB));
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@ -876,7 +874,22 @@ int css_do_tsch(SubchDev *sch, IRB *target_irb)
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}
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}
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/* Store the irb to the guest. */
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copy_irb_to_guest(target_irb, &irb, p);
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copy_irb_to_guest(target_irb, &irb, p, irb_len);
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return ((stctl & SCSW_STCTL_STATUS_PEND) == 0);
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}
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void css_do_tsch_update_subch(SubchDev *sch)
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{
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SCSW *s = &sch->curr_status.scsw;
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PMCW *p = &sch->curr_status.pmcw;
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uint16_t stctl;
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uint16_t fctl;
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uint16_t actl;
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stctl = s->ctrl & SCSW_CTRL_MASK_STCTL;
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fctl = s->ctrl & SCSW_CTRL_MASK_FCTL;
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actl = s->ctrl & SCSW_CTRL_MASK_ACTL;
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/* Clear conditions on subchannel, if applicable. */
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if (stctl & SCSW_STCTL_STATUS_PEND) {
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@ -913,11 +926,6 @@ int css_do_tsch(SubchDev *sch, IRB *target_irb)
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memset(sch->sense_data, 0 , sizeof(sch->sense_data));
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}
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}
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ret = ((stctl & SCSW_STCTL_STATUS_PEND) == 0);
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out:
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return ret;
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}
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static void copy_crw_to_guest(CRW *dest, const CRW *src)
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@ -455,7 +455,8 @@ int css_do_xsch(SubchDev *sch);
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int css_do_csch(SubchDev *sch);
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int css_do_hsch(SubchDev *sch);
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int css_do_ssch(SubchDev *sch, ORB *orb);
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int css_do_tsch(SubchDev *sch, IRB *irb);
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int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
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void css_do_tsch_update_subch(SubchDev *sch);
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int css_do_stcrw(CRW *crw);
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int css_do_tpi(IOIntCode *int_code, int lowcore);
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int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
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@ -341,10 +341,9 @@ int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
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CPUS390XState *env = &cpu->env;
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int cssid, ssid, schid, m;
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SubchDev *sch;
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IRB *irb;
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IRB irb;
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uint64_t addr;
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int cc;
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hwaddr len = sizeof(*irb);
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int cc, irb_len;
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if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
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program_interrupt(env, PGM_OPERAND, 2);
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@ -356,23 +355,29 @@ int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
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program_interrupt(env, PGM_SPECIFICATION, 2);
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return -EIO;
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}
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irb = s390_cpu_physical_memory_map(env, addr, &len, 1);
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if (!irb || len != sizeof(*irb)) {
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program_interrupt(env, PGM_ADDRESSING, 2);
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cc = -EIO;
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goto out;
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}
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sch = css_find_subch(m, cssid, ssid, schid);
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if (sch && css_subch_visible(sch)) {
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cc = css_do_tsch(sch, irb);
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/* 0 - status pending, 1 - not status pending */
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cc = css_do_tsch_get_irb(sch, &irb, &irb_len);
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} else {
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cc = 3;
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}
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/* 0 - status pending, 1 - not status pending, 3 - not operational */
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if (cc != 3) {
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if (s390_cpu_virt_mem_write(cpu, addr, &irb, irb_len) != 0) {
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return -EFAULT;
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}
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css_do_tsch_update_subch(sch);
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} else {
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irb_len = sizeof(irb) - sizeof(irb.emw);
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/* Access exceptions have a higher priority than cc3 */
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if (s390_cpu_virt_mem_check_write(cpu, addr, irb_len) != 0) {
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return -EFAULT;
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}
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}
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setcc(cpu, cc);
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out:
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s390_cpu_physical_memory_unmap(env, irb, sizeof(*irb), 1);
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return cc;
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return 0;
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}
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typedef struct ChscReq {
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