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target/arm: Introduce arm_hcr_el2_eff_secstate

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For page walking, we may require HCR for a security state
that is not "current".

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-10-01 09:22:49 -07:00 committed by Peter Maydell
parent fdf1293339
commit b74c04431d
2 changed files with 21 additions and 10 deletions
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20
target/arm/cpu.h
View File

@ -2412,15 +2412,15 @@ static inline bool arm_is_secure(CPUARMState *env)
* Return true if the current security state has AArch64 EL2 or AArch32 Hyp. * Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
* This corresponds to the pseudocode EL2Enabled() * This corresponds to the pseudocode EL2Enabled()
*/ */
static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
{
return arm_feature(env, ARM_FEATURE_EL2)
&& (!secure || (env->cp15.scr_el3 & SCR_EEL2));
}
static inline bool arm_is_el2_enabled(CPUARMState *env) static inline bool arm_is_el2_enabled(CPUARMState *env)
{ {
if (arm_feature(env, ARM_FEATURE_EL2)) { return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env));
if (arm_is_secure_below_el3(env)) {
return (env->cp15.scr_el3 & SCR_EEL2) != 0;
}
return true;
}
return false;
} }
#else #else
@ -2434,6 +2434,11 @@ static inline bool arm_is_secure(CPUARMState *env)
return false; return false;
} }
static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
{
return false;
}
static inline bool arm_is_el2_enabled(CPUARMState *env) static inline bool arm_is_el2_enabled(CPUARMState *env)
{ {
return false; return false;
@ -2446,6 +2451,7 @@ static inline bool arm_is_el2_enabled(CPUARMState *env)
* "for all purposes other than a direct read or write access of HCR_EL2." * "for all purposes other than a direct read or write access of HCR_EL2."
* Not included here is HCR_RW. * Not included here is HCR_RW.
*/ */
uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure);
uint64_t arm_hcr_el2_eff(CPUARMState *env); uint64_t arm_hcr_el2_eff(CPUARMState *env);
uint64_t arm_hcrx_el2_eff(CPUARMState *env); uint64_t arm_hcrx_el2_eff(CPUARMState *env);

11
target/arm/helper.c
View File

@ -5229,15 +5229,15 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
} }
/* /*
* Return the effective value of HCR_EL2. * Return the effective value of HCR_EL2, at the given security state.
* Bits that are not included here: * Bits that are not included here:
* RW (read from SCR_EL3.RW as needed) * RW (read from SCR_EL3.RW as needed)
*/ */
uint64_t arm_hcr_el2_eff(CPUARMState *env) uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure)
{ {
uint64_t ret = env->cp15.hcr_el2; uint64_t ret = env->cp15.hcr_el2;
if (!arm_is_el2_enabled(env)) { if (!arm_is_el2_enabled_secstate(env, secure)) {
/* /*
* "This register has no effect if EL2 is not enabled in the * "This register has no effect if EL2 is not enabled in the
* current Security state". This is ARMv8.4-SecEL2 speak for * current Security state". This is ARMv8.4-SecEL2 speak for
@ -5296,6 +5296,11 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
return ret; return ret;
} }
uint64_t arm_hcr_el2_eff(CPUARMState *env)
{
return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env));
}
/* /*
* Corresponds to ARM pseudocode function ELIsInHost(). * Corresponds to ARM pseudocode function ELIsInHost().
*/ */