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pnv/psi: Allow access to PSI registers through xscom

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skiboot only uses mmio to access the PSI registers (once the BAR is
set) but we don't have any reason to block the accesses through
xscom. This patch enables xscom access to the PSI registers. It
converts the xscom addresses to mmio addresses, which requires a bit
of care for the PSIHB, then reuse the existing mmio ops.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230630102609.193214-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Frederic Barrat 2023-06-30 12:26:09 +02:00 committed by Daniel Henrique Barboza
parent 97c81ef4b8
commit b5ea6754e8
1 changed files with 21 additions and 10 deletions
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31
hw/ppc/pnv_psi.c
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@ -121,8 +121,12 @@
#define PSIHB9_BAR_MASK 0x00fffffffff00000ull
#define PSIHB9_FSPBAR_MASK 0x00ffffff00000000ull
/* mmio address to xscom address */
#define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR)
/* xscom address to mmio address */
#define PSIHB_MMIO(reg) ((reg - PSIHB_XSCOM_BAR) << 3)
static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
{
PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi);
@ -769,24 +773,31 @@ static const MemoryRegionOps pnv_psi_p9_mmio_ops = {
static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size)
{
/* No read are expected */
qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom read at 0x%" PRIx64 "\n", addr);
return -1;
uint32_t reg = addr >> 3;
uint64_t val = -1;
if (reg < PSIHB_XSCOM_BAR) {
/* FIR, not modeled */
qemu_log_mask(LOG_UNIMP, "PSI: xscom read at 0x%08x\n", reg);
} else {
val = pnv_psi_p9_mmio_read(opaque, PSIHB_MMIO(reg), size);
}
return val;
}
static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PnvPsi *psi = PNV_PSI(opaque);
uint32_t reg = addr >> 3;
/* XSCOM is only used to set the PSIHB MMIO region */
switch (addr >> 3) {
case PSIHB_XSCOM_BAR:
if (reg < PSIHB_XSCOM_BAR) {
/* FIR, not modeled */
qemu_log_mask(LOG_UNIMP, "PSI: xscom write at 0x%08x\n", reg);
} else if (reg == PSIHB_XSCOM_BAR) {
pnv_psi_set_bar(psi, val);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom write at 0x%" PRIx64 "\n",
addr);
} else {
pnv_psi_p9_mmio_write(opaque, PSIHB_MMIO(reg), val, size);
}
}