xilinx_spips: Trash LQ page cache on mode change
Invalidate the LQSPI cached page when transitioning into LQSPI mode. Otherwise there is a possibility that the controller will return stale data to the guest when transitioning back to LQ_MODE after a page program. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 677490a6ee1953fe5d366e599d665de645ac84db.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -165,6 +165,8 @@ typedef struct {
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typedef struct XilinxSPIPSClass {
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SysBusDeviceClass parent_class;
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const MemoryRegionOps *reg_ops;
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uint32_t rx_fifo_size;
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uint32_t tx_fifo_size;
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} XilinxSPIPSClass;
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@ -462,6 +464,25 @@ static const MemoryRegionOps spips_ops = {
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void xilinx_qspips_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
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xilinx_spips_write(opaque, addr, value, size);
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addr >>= 2;
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if (addr == R_LQSPI_CFG) {
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q->lqspi_cached_addr = ~0ULL;
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}
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}
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static const MemoryRegionOps qspips_ops = {
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.read = xilinx_spips_read,
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.write = xilinx_qspips_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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#define LQSPI_CACHE_SIZE 1024
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static uint64_t
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@ -565,7 +586,7 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp)
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sysbus_init_irq(sbd, &s->cs_lines[i]);
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}
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memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4);
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memory_region_init_io(&s->iomem, xsc->reg_ops, s, "spi", R_MAX*4);
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sysbus_init_mmio(sbd, &s->iomem);
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s->irqline = -1;
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@ -629,6 +650,7 @@ static void xilinx_qspips_class_init(ObjectClass *klass, void * data)
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XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
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dc->realize = xilinx_qspips_realize;
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xsc->reg_ops = &qspips_ops;
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xsc->rx_fifo_size = RXFF_A_Q;
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xsc->tx_fifo_size = TXFF_A_Q;
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}
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@ -643,6 +665,7 @@ static void xilinx_spips_class_init(ObjectClass *klass, void *data)
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dc->props = xilinx_spips_properties;
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dc->vmsd = &vmstate_xilinx_spips;
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xsc->reg_ops = &spips_ops;
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xsc->rx_fifo_size = RXFF_A;
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xsc->tx_fifo_size = TXFF_A;
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}
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