target/arm: Make functions used by translate-neon global
Make the remaining functions needed by the translate-neon code global. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210430132740.10391-13-peter.maydell@linaro.org
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@ -39,6 +39,8 @@ void gen_set_pc_im(DisasContext *s, target_ulong val);
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void gen_lookup_tb(DisasContext *s);
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long vfp_reg_offset(bool dp, unsigned reg);
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long neon_full_reg_offset(unsigned reg);
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long neon_element_offset(int reg, int element, MemOp memop);
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void gen_rev16(TCGv_i32 dest, TCGv_i32 var);
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static inline TCGv_i32 load_cpu_offset(int offset)
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{
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@ -130,4 +132,10 @@ DO_GEN_ST(32, MO_UL)
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/* Set NZCV flags from the high 4 bits of var. */
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#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
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/* Swap low and high halfwords. */
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static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
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{
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tcg_gen_rotri_i32(dest, var, 16);
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}
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#endif
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@ -325,7 +325,7 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
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}
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/* Byteswap each halfword. */
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static void gen_rev16(TCGv_i32 dest, TCGv_i32 var)
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void gen_rev16(TCGv_i32 dest, TCGv_i32 var)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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TCGv_i32 mask = tcg_const_i32(0x00ff00ff);
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@ -346,12 +346,6 @@ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var)
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tcg_gen_ext16s_i32(dest, var);
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}
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/* Swap low and high halfwords. */
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static void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
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{
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tcg_gen_rotri_i32(dest, var, 16);
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}
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/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
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tmp = (t0 ^ t1) & 0x8000;
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t0 &= ~0x8000;
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@ -1104,7 +1098,7 @@ long neon_full_reg_offset(unsigned reg)
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* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
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* where 0 is the least significant end of the register.
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*/
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static long neon_element_offset(int reg, int element, MemOp memop)
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long neon_element_offset(int reg, int element, MemOp memop)
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{
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int element_size = 1 << (memop & MO_SIZE);
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int ofs = element * element_size;
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