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Clean up VGA ram allocation.

Browse Source 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7063 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook 2009-04-10 02:24:36 +00:00
parent a8b01dd87f
commit b584726df9
16 changed files with 71 additions and 130 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
hw/cirrus_vga.c
View File

@ -3289,15 +3289,13 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
*
***************************************/
void isa_cirrus_vga_init(uint8_t *vga_ram_base,
ram_addr_t vga_ram_offset, int vga_ram_size)
void isa_cirrus_vga_init(int vga_ram_size)
{
CirrusVGAState *s;
s = qemu_mallocz(sizeof(CirrusVGAState));
vga_common_init((VGAState *)s,
vga_ram_base, vga_ram_offset, vga_ram_size);
vga_common_init((VGAState *)s, vga_ram_size);
cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);
@ -3358,8 +3356,7 @@ static void pci_cirrus_write_config(PCIDevice *d,
vga_dirty_log_start((VGAState *)s);
}
void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
ram_addr_t vga_ram_offset, int vga_ram_size)
void pci_cirrus_vga_init(PCIBus *bus, int vga_ram_size)
{
PCICirrusVGAState *d;
uint8_t *pci_conf;
@ -3381,8 +3378,7 @@ void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
/* setup VGA */
s = &d->cirrus_vga;
vga_common_init((VGAState *)s,
vga_ram_base, vga_ram_offset, vga_ram_size);
vga_common_init((VGAState *)s, vga_ram_size);
cirrus_init_common(s, device_id, 1);
s->ds = graphic_console_init(s->update, s->invalidate,

7
hw/g364fb.c
View File

@ -584,8 +584,7 @@ static void g364fb_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, s->height);
}
int g364fb_mm_init(uint8_t *vram, ram_addr_t vram_offset,
int vram_size, target_phys_addr_t vram_base,
int g364fb_mm_init(int vram_size, target_phys_addr_t vram_base,
target_phys_addr_t ctrl_base, int it_shift,
qemu_irq irq)
{
@ -594,8 +593,8 @@ int g364fb_mm_init(uint8_t *vram, ram_addr_t vram_offset,
s = qemu_mallocz(sizeof(G364State));
s->vram = vram;
s->vram_offset = vram_offset;
s->vram_offset = qemu_ram_alloc(vram_size);
s->vram = qemu_get_ram_ptr(s->vram_offset);
s->vram_size = vram_size;
s->irq = irq;

3
hw/mips.h
View File

@ -10,8 +10,7 @@ void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
void ds1225y_set_protection(void *opaque, int protection);
/* g364fb.c */
int g364fb_mm_init(uint8_t *vram, ram_addr_t vram_offset,
int vram_size, target_phys_addr_t vram_base,
int g364fb_mm_init(int vram_size, target_phys_addr_t vram_base,
target_phys_addr_t ctrl_base, int it_shift,
qemu_irq irq);

8
hw/mips_jazz.c
View File

@ -142,7 +142,6 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
qemu_irq esp_reset;
ram_addr_t ram_offset;
ram_addr_t bios_offset;
ram_addr_t vga_ram_offset;
/* init CPUs */
if (cpu_model == NULL) {
@ -164,7 +163,6 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
ram_offset = qemu_ram_alloc(ram_size);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
vga_ram_offset = qemu_ram_alloc(vga_ram_size);
bios_offset = qemu_ram_alloc(MAGNUM_BIOS_SIZE);
cpu_register_physical_memory(0x1fc00000LL,
MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
@ -205,12 +203,10 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
/* Video card */
switch (jazz_model) {
case JAZZ_MAGNUM:
g364fb_mm_init(phys_ram_base + vga_ram_offset, ram_size, vga_ram_size,
0x40000000, 0x60000000, 0, rc4030[3]);
g364fb_mm_init(vga_ram_size, 0x40000000, 0x60000000, 0, rc4030[3]);
break;
case JAZZ_PICA61:
isa_vga_mm_init(phys_ram_base + vga_ram_offset, ram_size, vga_ram_size,
0x40000000, 0x60000000, 0);
isa_vga_mm_init(vga_ram_size, 0x40000000, 0x60000000, 0);
break;
default:
break;

11
hw/mips_malta.c
View File

@ -769,7 +769,6 @@ void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
{
char buf[1024];
ram_addr_t ram_offset;
ram_addr_t vga_ram_offset;
ram_addr_t bios_offset;
target_long bios_size;
int64_t kernel_entry;
@ -812,7 +811,6 @@ void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
exit(1);
}
ram_offset = qemu_ram_alloc(ram_size);
vga_ram_offset = qemu_ram_alloc(vga_ram_size);
bios_offset = qemu_ram_alloc(BIOS_SIZE);
@ -949,14 +947,11 @@ void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
/* Optional PCI video card */
if (cirrus_vga_enabled) {
pci_cirrus_vga_init(pci_bus, phys_ram_base + vga_ram_offset,
ram_size, vga_ram_size);
pci_cirrus_vga_init(pci_bus, vga_ram_size);
} else if (vmsvga_enabled) {
pci_vmsvga_init(pci_bus, phys_ram_base + vga_ram_offset,
ram_size, vga_ram_size);
pci_vmsvga_init(pci_bus, vga_ram_size);
} else if (std_vga_enabled) {
pci_vga_init(pci_bus, phys_ram_base + vga_ram_offset,
ram_size, vga_ram_size, 0, 0);
pci_vga_init(pci_bus, vga_ram_size, 0, 0);
}
}

5
hw/mips_r4k.c
View File

@ -155,7 +155,6 @@ void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size,
{
char buf[1024];
ram_addr_t ram_offset;
ram_addr_t vga_ram_offset;
ram_addr_t bios_offset;
int bios_size;
CPUState *env;
@ -188,7 +187,6 @@ void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size,
exit(1);
}
ram_offset = qemu_ram_alloc(ram_size);
vga_ram_offset = qemu_ram_alloc(vga_ram_size);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
@ -257,8 +255,7 @@ void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size,
}
}
isa_vga_init(phys_ram_base + vga_ram_offset, ram_size,
vga_ram_size);
isa_vga_init(vga_ram_size);
if (nd_table[0].vlan)
isa_ne2000_init(0x300, i8259[9], &nd_table[0]);

21
hw/pc.c
View File

@ -784,7 +784,7 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
{
char buf[1024];
int ret, linux_boot, i;
ram_addr_t ram_addr, vga_ram_addr, bios_offset, option_rom_offset;
ram_addr_t ram_addr, bios_offset, option_rom_offset;
ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
int bios_size, isa_bios_size, oprom_area_size;
PCIBus *pci_bus;
@ -858,9 +858,6 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
}
/* allocate VGA RAM */
vga_ram_addr = qemu_ram_alloc(vga_ram_size);
/* BIOS load */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
@ -943,26 +940,20 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
if (cirrus_vga_enabled) {
if (pci_enabled) {
pci_cirrus_vga_init(pci_bus,
phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size);
pci_cirrus_vga_init(pci_bus, vga_ram_size);
} else {
isa_cirrus_vga_init(phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size);
isa_cirrus_vga_init(vga_ram_size);
}
} else if (vmsvga_enabled) {
if (pci_enabled)
pci_vmsvga_init(pci_bus, phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size);
pci_vmsvga_init(pci_bus, vga_ram_size);
else
fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
} else if (std_vga_enabled) {
if (pci_enabled) {
pci_vga_init(pci_bus, phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size, 0, 0);
pci_vga_init(pci_bus, vga_ram_size, 0, 0);
} else {
isa_vga_init(phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size);
isa_vga_init(vga_ram_size);
}
}

18
hw/pc.h
View File

@ -144,21 +144,15 @@ extern enum vga_retrace_method vga_retrace_method;
#define VGA_RAM_SIZE (9 * 1024 * 1024)
#endif
int isa_vga_init(uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size);
int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size,
int isa_vga_init(int vga_ram_size);
int pci_vga_init(PCIBus *bus, int vga_ram_size,
unsigned long vga_bios_offset, int vga_bios_size);
int isa_vga_mm_init(uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size,
target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
int it_shift);
int isa_vga_mm_init(int vga_ram_size, target_phys_addr_t vram_base,
target_phys_addr_t ctrl_base, int it_shift);
/* cirrus_vga.c */
void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
ram_addr_t vga_ram_offset, int vga_ram_size);
void isa_cirrus_vga_init(uint8_t *vga_ram_base,
ram_addr_t vga_ram_offset, int vga_ram_size);
void pci_cirrus_vga_init(PCIBus *bus, int vga_ram_size);
void isa_cirrus_vga_init(int vga_ram_size);
/* ide.c */
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,

3
hw/pci.h
View File

@ -219,8 +219,7 @@ void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
void *lsi_scsi_init(PCIBus *bus, int devfn);
/* vmware_vga.c */
void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size);
void pci_vmsvga_init(PCIBus *bus, int vga_ram_size);
/* usb-uhci.c */
void usb_uhci_piix3_init(PCIBus *bus, int devfn);

8
hw/ppc_newworld.c
View File

@ -97,7 +97,7 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
qemu_irq *pic, **openpic_irqs;
int unin_memory;
int linux_boot, i;
ram_addr_t ram_offset, vga_ram_offset, bios_offset, vga_bios_offset;
ram_addr_t ram_offset, bios_offset, vga_bios_offset;
uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
PCIBus *pci_bus;
MacIONVRAMState *nvr;
@ -136,9 +136,6 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
ram_offset = qemu_ram_alloc(ram_size);
cpu_register_physical_memory(0, ram_size, ram_offset);
/* allocate VGA RAM */
vga_ram_offset = qemu_ram_alloc(vga_ram_size);
/* allocate and load BIOS */
bios_offset = qemu_ram_alloc(BIOS_SIZE);
if (bios_name == NULL)
@ -288,8 +285,7 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL);
pci_bus = pci_pmac_init(pic);
/* init basic PC hardware */
pci_vga_init(pci_bus, phys_ram_base + vga_ram_offset,
vga_ram_offset, vga_ram_size,
pci_vga_init(pci_bus, vga_ram_size,
vga_bios_offset, vga_bios_size);
/* XXX: suppress that */

8
hw/ppc_oldworld.c
View File

@ -125,7 +125,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
char buf[1024];
qemu_irq *pic, **heathrow_irqs;
int linux_boot, i;
ram_addr_t ram_offset, vga_ram_offset, bios_offset, vga_bios_offset;
ram_addr_t ram_offset, bios_offset, vga_bios_offset;
uint32_t kernel_base, initrd_base;
int32_t kernel_size, initrd_size;
PCIBus *pci_bus;
@ -169,9 +169,6 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
ram_offset = qemu_ram_alloc(ram_size);
cpu_register_physical_memory(0, ram_size, ram_offset);
/* allocate VGA RAM */
vga_ram_offset = qemu_ram_alloc(vga_ram_size);
/* allocate and load BIOS */
bios_offset = qemu_ram_alloc(BIOS_SIZE);
if (bios_name == NULL)
@ -303,8 +300,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
}
pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
pci_bus = pci_grackle_init(0xfec00000, pic);
pci_vga_init(pci_bus, phys_ram_base + vga_ram_offset,
vga_ram_offset, vga_ram_size,
pci_vga_init(pci_bus, vga_ram_size,
vga_bios_offset, vga_bios_size);
escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],

8
hw/ppc_prep.c
View File

@ -543,7 +543,7 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
m48t59_t *m48t59;
int PPC_io_memory;
int linux_boot, i, nb_nics1, bios_size;
ram_addr_t ram_offset, vga_ram_offset, bios_offset;
ram_addr_t ram_offset, bios_offset;
uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
PCIBus *pci_bus;
qemu_irq *i8259;
@ -580,9 +580,6 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
ram_offset = qemu_ram_alloc(ram_size);
cpu_register_physical_memory(0, ram_size, ram_offset);
/* allocate VGA RAM */
vga_ram_offset = qemu_ram_alloc(vga_ram_size);
/* allocate and load BIOS */
bios_offset = qemu_ram_alloc(BIOS_SIZE);
if (bios_name == NULL)
@ -663,8 +660,7 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
/* init basic PC hardware */
pci_vga_init(pci_bus, phys_ram_base + vga_ram_offset,
vga_ram_offset, vga_ram_size, 0, 0);
pci_vga_init(pci_bus, vga_ram_size, 0, 0);
// openpic = openpic_init(0x00000000, 0xF0000000, 1);
// pit = pit_init(0x40, i8259[0]);
rtc_init(0x70, i8259[8], 2000);

7
hw/sun4u.c
View File

@ -337,7 +337,7 @@ static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
m48t59_t *nvram;
int ret, linux_boot;
unsigned int i;
ram_addr_t ram_offset, prom_offset, vga_ram_offset;
ram_addr_t ram_offset, prom_offset;
long initrd_size, kernel_size;
PCIBus *pci_bus, *pci_bus2, *pci_bus3;
QEMUBH *bh;
@ -447,10 +447,7 @@ static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL, &pci_bus2,
&pci_bus3);
isa_mem_base = VGA_BASE;
vga_ram_offset = qemu_ram_alloc(vga_ram_size);
pci_vga_init(pci_bus, phys_ram_base + vga_ram_offset,
vga_ram_offset, vga_ram_size,
0, 0);
pci_vga_init(pci_bus, vga_ram_size, 0, 0);
// XXX Should be pci_bus3
pci_ebus_init(pci_bus, -1);

29
hw/vga.c
View File

@ -2266,8 +2266,7 @@ static void vga_map(PCIDevice *pci_dev, int region_num,
vga_dirty_log_start(s);
}
void vga_common_init(VGAState *s, uint8_t *vga_ram_base,
ram_addr_t vga_ram_offset, int vga_ram_size)
void vga_common_init(VGAState *s, int vga_ram_size)
{
int i, j, v, b;
@ -2294,8 +2293,8 @@ void vga_common_init(VGAState *s, uint8_t *vga_ram_base,
expand4to8[i] = v;
}
s->vram_ptr = vga_ram_base;
s->vram_offset = vga_ram_offset;
s->vram_offset = qemu_ram_alloc(vga_ram_size);
s->vram_ptr = qemu_get_ram_ptr(s->vram_offset);
s->vram_size = vga_ram_size;
s->get_bpp = vga_get_bpp;
s->get_offsets = vga_get_offsets;
@ -2445,14 +2444,13 @@ static void vga_mm_init(VGAState *s, target_phys_addr_t vram_base,
qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000);
}
int isa_vga_init(uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size)
int isa_vga_init(int vga_ram_size)
{
VGAState *s;
s = qemu_mallocz(sizeof(VGAState));
vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_common_init(s, vga_ram_size);
vga_init(s);
s->ds = graphic_console_init(s->update, s->invalidate,
@ -2461,21 +2459,19 @@ int isa_vga_init(uint8_t *vga_ram_base,
#ifdef CONFIG_BOCHS_VBE
/* XXX: use optimized standard vga accesses */
cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
vga_ram_size, vga_ram_offset);
vga_ram_size, s->vram_offset);
#endif
return 0;
}
int isa_vga_mm_init(uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size,
target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
int it_shift)
int isa_vga_mm_init(int vga_ram_size, target_phys_addr_t vram_base,
target_phys_addr_t ctrl_base, int it_shift)
{
VGAState *s;
s = qemu_mallocz(sizeof(VGAState));
vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_common_init(s, vga_ram_size);
vga_mm_init(s, vram_base, ctrl_base, it_shift);
s->ds = graphic_console_init(s->update, s->invalidate,
@ -2484,7 +2480,7 @@ int isa_vga_mm_init(uint8_t *vga_ram_base,
#ifdef CONFIG_BOCHS_VBE
/* XXX: use optimized standard vga accesses */
cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
vga_ram_size, vga_ram_offset);
vga_ram_size, s->vram_offset);
#endif
return 0;
}
@ -2500,8 +2496,7 @@ static void pci_vga_write_config(PCIDevice *d,
vga_dirty_log_start(s);
}
int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size,
int pci_vga_init(PCIBus *bus, int vga_ram_size,
unsigned long vga_bios_offset, int vga_bios_size)
{
PCIVGAState *d;
@ -2515,7 +2510,7 @@ int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
return -1;
s = &d->vga_state;
vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_common_init(s, vga_ram_size);
vga_init(s);
s->ds = graphic_console_init(s->update, s->invalidate,

3
hw/vga_int.h
View File

@ -191,8 +191,7 @@ static inline int c6_to_8(int v)
return (v << 2) | (b << 1) | b;
}
void vga_common_init(VGAState *s, uint8_t *vga_ram_base,
ram_addr_t vga_ram_offset, int vga_ram_size);
void vga_common_init(VGAState *s, int vga_ram_size);
void vga_init(VGAState *s);
void vga_reset(void *s);

50
hw/vmware_vga.c
View File

@ -59,8 +59,8 @@ struct vmsvga_state_s {
DisplayState *ds;
int vram_size;
ram_addr_t vram_offset;
uint8_t *vram_ptr;
#endif
uint8_t *vram;
target_phys_addr_t vram_base;
int index;
@ -326,7 +326,7 @@ static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
bypl = s->bypp * s->width;
width = s->bypp * w;
start = s->bypp * x + bypl * y;
src = s->vram + start;
src = s->vram_ptr + start;
dst = ds_get_data(s->ds) + start;
for (; line > 0; line --, src += bypl, dst += bypl)
@ -339,7 +339,7 @@ static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
{
#ifndef DIRECT_VRAM
memcpy(ds_get_data(s->ds), s->vram, s->bypp * s->width * s->height);
memcpy(ds_get_data(s->ds), s->vram_ptr, s->bypp * s->width * s->height);
#endif
dpy_update(s->ds, 0, 0, s->width, s->height);
@ -383,7 +383,7 @@ static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
# ifdef DIRECT_VRAM
uint8_t *vram = ds_get_data(s->ds);
# else
uint8_t *vram = s->vram;
uint8_t *vram = s->vram_ptr;
# endif
int bypl = s->bypp * s->width;
int width = s->bypp * w;
@ -420,7 +420,7 @@ static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
# ifdef DIRECT_VRAM
uint8_t *vram = ds_get_data(s->ds);
# else
uint8_t *vram = s->vram;
uint8_t *vram = s->vram_ptr;
# endif
int bypp = s->bypp;
int bypl = bypp * s->width;
@ -801,7 +801,7 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
case SVGA_REG_CONFIG_DONE:
if (value) {
s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
s->fifo = (uint32_t *) &s->vram_ptr[s->vram_size - SVGA_FIFO_SIZE];
/* Check range and alignment. */
if ((CMD(min) | CMD(max) |
CMD(next_cmd) | CMD(stop)) & 3)
@ -985,7 +985,7 @@ static void vmsvga_screen_dump(void *opaque, const char *filename)
if (s->depth == 32) {
DisplaySurface *ds = qemu_create_displaysurface_from(s->width,
s->height, 32, ds_get_linesize(s->ds), s->vram);
s->height, 32, ds_get_linesize(s->ds), s->vram_ptr);
ppm_save(filename, ds);
qemu_free(ds);
}
@ -1006,7 +1006,7 @@ static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
if (addr < s->fb_size)
return *(uint8_t *) (ds_get_data(s->ds) + addr);
else
return *(uint8_t *) (s->vram + addr);
return *(uint8_t *) (s->vram_ptr + addr);
}
static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
@ -1015,7 +1015,7 @@ static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
if (addr < s->fb_size)
return *(uint16_t *) (ds_get_data(s->ds) + addr);
else
return *(uint16_t *) (s->vram + addr);
return *(uint16_t *) (s->vram_ptr + addr);
}
static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
@ -1024,7 +1024,7 @@ static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
if (addr < s->fb_size)
return *(uint32_t *) (ds_get_data(s->ds) + addr);
else
return *(uint32_t *) (s->vram + addr);
return *(uint32_t *) (s->vram_ptr + addr);
}
static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
@ -1034,7 +1034,7 @@ static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
if (addr < s->fb_size)
*(uint8_t *) (ds_get_data(s->ds) + addr) = value;
else
*(uint8_t *) (s->vram + addr) = value;
*(uint8_t *) (s->vram_ptr + addr) = value;
}
static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
@ -1044,7 +1044,7 @@ static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
if (addr < s->fb_size)
*(uint16_t *) (ds_get_data(s->ds) + addr) = value;
else
*(uint16_t *) (s->vram + addr) = value;
*(uint16_t *) (s->vram_ptr + addr) = value;
}
static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
@ -1054,7 +1054,7 @@ static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
if (addr < s->fb_size)
*(uint32_t *) (ds_get_data(s->ds) + addr) = value;
else
*(uint32_t *) (s->vram + addr) = value;
*(uint32_t *) (s->vram_ptr + addr) = value;
}
static CPUReadMemoryFunc *vmsvga_vram_read[] = {
@ -1116,28 +1116,25 @@ static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
s->invalidated = 1;
if (s->config)
s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
s->fifo = (uint32_t *) &s->vram_ptr[s->vram_size - SVGA_FIFO_SIZE];
return 0;
}
static void vmsvga_init(struct vmsvga_state_s *s,
uint8_t *vga_ram_base, unsigned long vga_ram_offset,
int vga_ram_size)
static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
{
s->vram = vga_ram_base;
s->vram_size = vga_ram_size;
s->vram_offset = vga_ram_offset;
s->scratch_size = SVGA_SCRATCH_SIZE;
s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
vmsvga_reset(s);
#ifdef EMBED_STDVGA
vga_common_init((VGAState *) s,
vga_ram_base, vga_ram_offset, vga_ram_size);
vga_common_init((VGAState *) s, vga_ram_size);
vga_init((VGAState *) s);
#else
s->vram_size = vga_ram_size;
s->vram_offset = qemu_ram_alloc(vga_ram_size);
s->vram_ptr = qemu_get_ram_ptr(s->vram_offset);
#endif
s->ds = graphic_console_init(vmsvga_update_display,
@ -1148,7 +1145,7 @@ static void vmsvga_init(struct vmsvga_state_s *s,
#ifdef CONFIG_BOCHS_VBE
/* XXX: use optimized standard vga accesses */
cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
vga_ram_size, vga_ram_offset);
vga_ram_size, s->vram_offset);
#endif
}
@ -1215,8 +1212,7 @@ static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
#define PCI_CLASS_HEADERTYPE_00h 0x00
void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size)
void pci_vmsvga_init(PCIBus *bus, int vga_ram_size)
{
struct pci_vmsvga_state_s *s;
@ -1242,7 +1238,7 @@ void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
pci_register_io_region(&s->card, 1, vga_ram_size,
PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem);
vmsvga_init(&s->chip, vga_ram_base, vga_ram_offset, vga_ram_size);
vmsvga_init(&s->chip, vga_ram_size);
register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);
}