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target/arm: Ignore PMCR.D when PMCR.LC is set

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The architecture requires that if PMCR.LC is set (for a 64-bit cycle
counter) then PMCR.D (which enables the clock divider so the counter
ticks every 64 cycles rather than every cycle) should be ignored.  We
were always honouring PMCR.D; fix the bug so we correctly ignore it
in this situation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-5-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell 2022-08-22 14:23:52 +01:00 committed by Richard Henderson
parent 01765386a8
commit b57aa7bdc3
1 changed files with 13 additions and 4 deletions
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17
target/arm/helper.c
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@ -1172,6 +1172,17 @@ static void pmu_update_irq(CPUARMState *env)
(env->cp15.c9_pminten & env->cp15.c9_pmovsr));
}
static bool pmccntr_clockdiv_enabled(CPUARMState *env)
{
/*
* Return true if the clock divider is enabled and the cycle counter
* is supposed to tick only once every 64 clock cycles. This is
* controlled by PMCR.D, but if PMCR.LC is set to enable the long
* (64-bit) cycle counter PMCR.D has no effect.
*/
return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) == PMCRD;
}
/*
* Ensure c15_ccnt is the guest-visible count so that operations such as
* enabling/disabling the counter or filtering, modifying the count itself,
@ -1184,8 +1195,7 @@ static void pmccntr_op_start(CPUARMState *env)
if (pmu_counter_enabled(env, 31)) {
uint64_t eff_cycles = cycles;
if (env->cp15.c9_pmcr & PMCRD) {
/* Increment once every 64 processor clock cycles */
if (pmccntr_clockdiv_enabled(env)) {
eff_cycles /= 64;
}
@ -1228,8 +1238,7 @@ static void pmccntr_op_finish(CPUARMState *env)
#endif
uint64_t prev_cycles = env->cp15.c15_ccnt_delta;
if (env->cp15.c9_pmcr & PMCRD) {
/* Increment once every 64 processor clock cycles */
if (pmccntr_clockdiv_enabled(env)) {
prev_cycles /= 64;
}
env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt;