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target/i386: Add support save/load HWCR MSR

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KVM commit 191c8137a939 ("x86/kvm: Implement HWCR support")
introduced support for emulating HWCR MSR.

Add support for QEMU to save/load this MSR for migration purposes.

Signed-off-by: Gao Shiyuan <gaoshiyuan@baidu.com>
Signed-off-by: Wang Liang <wangliang44@baidu.com>
Link: https://lore.kernel.org/r/20241009095109.66843-1-gaoshiyuan@baidu.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Gao Shiyuan 2024-10-09 17:51:09 +08:00 committed by Paolo Bonzini
parent 10eaf9c0fb
commit b5151ace58
3 changed files with 37 additions and 0 deletions
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5
target/i386/cpu.h
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@ -533,6 +533,8 @@ typedef enum X86Seg {
#define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL #define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL
#define MSR_K7_HWCR 0xc0010015
#define MSR_VM_HSAVE_PA 0xc0010117 #define MSR_VM_HSAVE_PA 0xc0010117
#define MSR_IA32_XFD 0x000001c4 #define MSR_IA32_XFD 0x000001c4
@ -1858,6 +1860,9 @@ typedef struct CPUArchState {
uint64_t msr_lbr_depth; uint64_t msr_lbr_depth;
LBREntry lbr_records[ARCH_LBR_NR_ENTRIES]; LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
/* AMD MSRC001_0015 Hardware Configuration */
uint64_t msr_hwcr;
/* exception/interrupt handling */ /* exception/interrupt handling */
int error_code; int error_code;
int exception_is_int; int exception_is_int;

12
target/i386/kvm/kvm.c
View File

@ -165,6 +165,7 @@ static bool has_msr_ucode_rev;
static bool has_msr_vmx_procbased_ctls2; static bool has_msr_vmx_procbased_ctls2;
static bool has_msr_perf_capabs; static bool has_msr_perf_capabs;
static bool has_msr_pkrs; static bool has_msr_pkrs;
static bool has_msr_hwcr;
static uint32_t has_architectural_pmu_version; static uint32_t has_architectural_pmu_version;
static uint32_t num_architectural_pmu_gp_counters; static uint32_t num_architectural_pmu_gp_counters;
@ -2577,6 +2578,8 @@ static int kvm_get_supported_msrs(KVMState *s)
case MSR_IA32_PKRS: case MSR_IA32_PKRS:
has_msr_pkrs = true; has_msr_pkrs = true;
break; break;
case MSR_K7_HWCR:
has_msr_hwcr = true;
} }
} }
} }
@ -3919,6 +3922,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
if (has_msr_virt_ssbd) { if (has_msr_virt_ssbd) {
kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd); kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
} }
if (has_msr_hwcr) {
kvm_msr_entry_add(cpu, MSR_K7_HWCR, env->msr_hwcr);
}
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
if (lm_capable_kernel) { if (lm_capable_kernel) {
@ -4403,6 +4409,9 @@ static int kvm_get_msrs(X86CPU *cpu)
kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0); kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
env->tsc_valid = !runstate_is_running(); env->tsc_valid = !runstate_is_running();
} }
if (has_msr_hwcr) {
kvm_msr_entry_add(cpu, MSR_K7_HWCR, 0);
}
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
if (lm_capable_kernel) { if (lm_capable_kernel) {
@ -4922,6 +4931,9 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31: case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31:
env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data; env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data;
break; break;
case MSR_K7_HWCR:
env->msr_hwcr = msrs[i].data;
break;
} }
} }

20
target/i386/machine.c
View File

@ -1543,6 +1543,25 @@ static const VMStateDescription vmstate_msr_xfd = {
} }
}; };
static bool msr_hwcr_needed(void *opaque)
{
X86CPU *cpu = opaque;
CPUX86State *env = &cpu->env;
return env->msr_hwcr != 0;
}
static const VMStateDescription vmstate_msr_hwcr = {
.name = "cpu/msr_hwcr",
.version_id = 1,
.minimum_version_id = 1,
.needed = msr_hwcr_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT64(env.msr_hwcr, X86CPU),
VMSTATE_END_OF_LIST()
}
};
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
static bool intel_fred_msrs_needed(void *opaque) static bool intel_fred_msrs_needed(void *opaque)
{ {
@ -1773,6 +1792,7 @@ const VMStateDescription vmstate_x86_cpu = {
&vmstate_msr_intel_sgx, &vmstate_msr_intel_sgx,
&vmstate_pdptrs, &vmstate_pdptrs,
&vmstate_msr_xfd, &vmstate_msr_xfd,
&vmstate_msr_hwcr,
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
&vmstate_msr_fred, &vmstate_msr_fred,
&vmstate_amx_xtile, &vmstate_amx_xtile,