hw/misc: Add a model of the Xilinx ZynqMP APU Control
Add a model of the Xilinx ZynqMP APU Control. Reviewed-by: Luc Michel <luc@lmichel.fr> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20220316164645.2303510-6-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Edgar E. Iglesias
Peter Maydell
parent
63320bcaed
commit
b4ecda2dd7
@ -85,6 +85,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
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softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
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softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
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specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
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specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
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softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
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'xlnx-versal-xramc.c',
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'xlnx-versal-pmc-iou-slcr.c',
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253
hw/misc/xlnx-zynqmp-apu-ctrl.c
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253
hw/misc/xlnx-zynqmp-apu-ctrl.c
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@ -0,0 +1,253 @@
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/*
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* QEMU model of the ZynqMP APU Control.
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*
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* Copyright (c) 2013-2022 Xilinx Inc
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
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* Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "migration/vmstate.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/register.h"
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#include "qemu/bitops.h"
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#include "qapi/qmp/qerror.h"
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#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
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#ifndef XILINX_ZYNQMP_APU_ERR_DEBUG
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#define XILINX_ZYNQMP_APU_ERR_DEBUG 0
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#endif
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static void update_wfi_out(void *opaque)
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{
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XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque);
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unsigned int i, wfi_pending;
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wfi_pending = s->cpu_pwrdwn_req & s->cpu_in_wfi;
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for (i = 0; i < APU_MAX_CPU; i++) {
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qemu_set_irq(s->wfi_out[i], !!(wfi_pending & (1 << i)));
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}
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}
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static void zynqmp_apu_rvbar_post_write(RegisterInfo *reg, uint64_t val)
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{
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XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
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int i;
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for (i = 0; i < APU_MAX_CPU; ++i) {
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uint64_t rvbar = s->regs[R_RVBARADDR0L + 2 * i] +
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((uint64_t)s->regs[R_RVBARADDR0H + 2 * i] << 32);
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if (s->cpus[i]) {
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object_property_set_int(OBJECT(s->cpus[i]), "rvbar", rvbar,
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&error_abort);
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}
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}
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}
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static void zynqmp_apu_pwrctl_post_write(RegisterInfo *reg, uint64_t val)
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{
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XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
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unsigned int i, new;
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for (i = 0; i < APU_MAX_CPU; i++) {
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new = val & (1 << i);
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/* Check if CPU's CPUPWRDNREQ has changed. If yes, update GPIOs. */
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if (new != (s->cpu_pwrdwn_req & (1 << i))) {
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qemu_set_irq(s->cpu_power_status[i], !!new);
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}
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s->cpu_pwrdwn_req &= ~(1 << i);
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s->cpu_pwrdwn_req |= new;
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}
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update_wfi_out(s);
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}
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static void imr_update_irq(XlnxZynqMPAPUCtrl *s)
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{
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bool pending = s->regs[R_ISR] & ~s->regs[R_IMR];
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qemu_set_irq(s->irq_imr, pending);
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}
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static void isr_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
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imr_update_irq(s);
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}
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static uint64_t ien_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
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uint32_t val = val64;
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s->regs[R_IMR] &= ~val;
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imr_update_irq(s);
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return 0;
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}
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static uint64_t ids_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
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uint32_t val = val64;
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s->regs[R_IMR] |= val;
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imr_update_irq(s);
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return 0;
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}
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static const RegisterAccessInfo zynqmp_apu_regs_info[] = {
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#define RVBAR_REGDEF(n) \
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{ .name = "RVBAR CPU " #n " Low", .addr = A_RVBARADDR ## n ## L, \
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.reset = 0xffff0000ul, \
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.post_write = zynqmp_apu_rvbar_post_write, \
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},{ .name = "RVBAR CPU " #n " High", .addr = A_RVBARADDR ## n ## H, \
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.post_write = zynqmp_apu_rvbar_post_write, \
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}
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{ .name = "ERR_CTRL", .addr = A_APU_ERR_CTRL,
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},{ .name = "ISR", .addr = A_ISR,
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.w1c = 0x1,
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.post_write = isr_postw,
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},{ .name = "IMR", .addr = A_IMR,
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.reset = 0x1,
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.ro = 0x1,
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},{ .name = "IEN", .addr = A_IEN,
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.pre_write = ien_prew,
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},{ .name = "IDS", .addr = A_IDS,
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.pre_write = ids_prew,
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},{ .name = "CONFIG_0", .addr = A_CONFIG_0,
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.reset = 0xf0f,
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},{ .name = "CONFIG_1", .addr = A_CONFIG_1,
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},
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RVBAR_REGDEF(0),
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RVBAR_REGDEF(1),
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RVBAR_REGDEF(2),
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RVBAR_REGDEF(3),
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{ .name = "ACE_CTRL", .addr = A_ACE_CTRL,
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.reset = 0xf000f,
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},{ .name = "SNOOP_CTRL", .addr = A_SNOOP_CTRL,
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},{ .name = "PWRCTL", .addr = A_PWRCTL,
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.post_write = zynqmp_apu_pwrctl_post_write,
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},{ .name = "PWRSTAT", .addr = A_PWRSTAT,
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.ro = 0x3000f,
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}
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};
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static void zynqmp_apu_reset_enter(Object *obj, ResetType type)
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{
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XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
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int i;
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for (i = 0; i < APU_R_MAX; ++i) {
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register_reset(&s->regs_info[i]);
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}
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s->cpu_pwrdwn_req = 0;
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s->cpu_in_wfi = 0;
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}
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static void zynqmp_apu_reset_hold(Object *obj)
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{
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XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
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update_wfi_out(s);
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imr_update_irq(s);
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}
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static const MemoryRegionOps zynqmp_apu_ops = {
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.read = register_read_memory,
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.write = register_write_memory,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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}
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};
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static void zynqmp_apu_handle_wfi(void *opaque, int irq, int level)
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{
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XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque);
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s->cpu_in_wfi = deposit32(s->cpu_in_wfi, irq, 1, level);
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update_wfi_out(s);
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}
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static void zynqmp_apu_init(Object *obj)
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{
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XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
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int i;
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s->reg_array =
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register_init_block32(DEVICE(obj), zynqmp_apu_regs_info,
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ARRAY_SIZE(zynqmp_apu_regs_info),
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s->regs_info, s->regs,
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&zynqmp_apu_ops,
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XILINX_ZYNQMP_APU_ERR_DEBUG,
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APU_R_MAX * 4);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->reg_array->mem);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq_imr);
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for (i = 0; i < APU_MAX_CPU; ++i) {
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g_autofree gchar *prop_name = g_strdup_printf("cpu%d", i);
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object_property_add_link(obj, prop_name, TYPE_ARM_CPU,
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(Object **)&s->cpus[i],
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qdev_prop_allow_set_link_before_realize,
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OBJ_PROP_LINK_STRONG);
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}
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/* wfi_out is used to connect to PMU GPIs. */
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qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 4);
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/* CPU_POWER_STATUS is used to connect to INTC redirect. */
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qdev_init_gpio_out_named(DEVICE(obj), s->cpu_power_status,
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"CPU_POWER_STATUS", 4);
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/* wfi_in is used as input from CPUs as wfi request. */
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qdev_init_gpio_in_named(DEVICE(obj), zynqmp_apu_handle_wfi, "wfi_in", 4);
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}
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static void zynqmp_apu_finalize(Object *obj)
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{
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XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
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register_finalize_block(s->reg_array);
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}
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static const VMStateDescription vmstate_zynqmp_apu = {
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.name = TYPE_XLNX_ZYNQMP_APU_CTRL,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPAPUCtrl, APU_R_MAX),
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VMSTATE_END_OF_LIST(),
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}
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};
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static void zynqmp_apu_class_init(ObjectClass *klass, void *data)
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{
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_zynqmp_apu;
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rc->phases.enter = zynqmp_apu_reset_enter;
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rc->phases.hold = zynqmp_apu_reset_hold;
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}
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static const TypeInfo zynqmp_apu_info = {
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.name = TYPE_XLNX_ZYNQMP_APU_CTRL,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(XlnxZynqMPAPUCtrl),
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.class_init = zynqmp_apu_class_init,
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.instance_init = zynqmp_apu_init,
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.instance_finalize = zynqmp_apu_finalize,
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};
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static void zynqmp_apu_register_types(void)
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{
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type_register_static(&zynqmp_apu_info);
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}
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type_init(zynqmp_apu_register_types)
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93
include/hw/misc/xlnx-zynqmp-apu-ctrl.h
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93
include/hw/misc/xlnx-zynqmp-apu-ctrl.h
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@ -0,0 +1,93 @@
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/*
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* QEMU model of ZynqMP APU Control.
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*
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* Copyright (c) 2013-2022 Xilinx Inc
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
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* Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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*
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*/
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#ifndef HW_MISC_XLNX_ZYNQMP_APU_CTRL_H
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#define HW_MISC_XLNX_ZYNQMP_APU_CTRL_H
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#include "target/arm/cpu.h"
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#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPAPUCtrl, XLNX_ZYNQMP_APU_CTRL)
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REG32(APU_ERR_CTRL, 0x0)
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FIELD(APU_ERR_CTRL, PSLVERR, 0, 1)
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REG32(ISR, 0x10)
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FIELD(ISR, INV_APB, 0, 1)
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REG32(IMR, 0x14)
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FIELD(IMR, INV_APB, 0, 1)
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REG32(IEN, 0x18)
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FIELD(IEN, INV_APB, 0, 1)
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REG32(IDS, 0x1c)
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FIELD(IDS, INV_APB, 0, 1)
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REG32(CONFIG_0, 0x20)
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FIELD(CONFIG_0, CFGTE, 24, 4)
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FIELD(CONFIG_0, CFGEND, 16, 4)
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FIELD(CONFIG_0, VINITHI, 8, 4)
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FIELD(CONFIG_0, AA64NAA32, 0, 4)
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REG32(CONFIG_1, 0x24)
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FIELD(CONFIG_1, L2RSTDISABLE, 29, 1)
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FIELD(CONFIG_1, L1RSTDISABLE, 28, 1)
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FIELD(CONFIG_1, CP15DISABLE, 0, 4)
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REG32(RVBARADDR0L, 0x40)
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FIELD(RVBARADDR0L, ADDR, 2, 30)
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REG32(RVBARADDR0H, 0x44)
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FIELD(RVBARADDR0H, ADDR, 0, 8)
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REG32(RVBARADDR1L, 0x48)
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FIELD(RVBARADDR1L, ADDR, 2, 30)
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REG32(RVBARADDR1H, 0x4c)
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FIELD(RVBARADDR1H, ADDR, 0, 8)
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REG32(RVBARADDR2L, 0x50)
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FIELD(RVBARADDR2L, ADDR, 2, 30)
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REG32(RVBARADDR2H, 0x54)
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FIELD(RVBARADDR2H, ADDR, 0, 8)
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REG32(RVBARADDR3L, 0x58)
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FIELD(RVBARADDR3L, ADDR, 2, 30)
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REG32(RVBARADDR3H, 0x5c)
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FIELD(RVBARADDR3H, ADDR, 0, 8)
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REG32(ACE_CTRL, 0x60)
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FIELD(ACE_CTRL, AWQOS, 16, 4)
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FIELD(ACE_CTRL, ARQOS, 0, 4)
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REG32(SNOOP_CTRL, 0x80)
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FIELD(SNOOP_CTRL, ACE_INACT, 4, 1)
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FIELD(SNOOP_CTRL, ACP_INACT, 0, 1)
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REG32(PWRCTL, 0x90)
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FIELD(PWRCTL, CLREXMONREQ, 17, 1)
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FIELD(PWRCTL, L2FLUSHREQ, 16, 1)
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FIELD(PWRCTL, CPUPWRDWNREQ, 0, 4)
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REG32(PWRSTAT, 0x94)
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FIELD(PWRSTAT, CLREXMONACK, 17, 1)
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FIELD(PWRSTAT, L2FLUSHDONE, 16, 1)
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FIELD(PWRSTAT, DBGNOPWRDWN, 0, 4)
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#define APU_R_MAX ((R_PWRSTAT) + 1)
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#define APU_MAX_CPU 4
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struct XlnxZynqMPAPUCtrl {
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SysBusDevice busdev;
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ARMCPU *cpus[APU_MAX_CPU];
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/* WFIs towards PMU. */
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qemu_irq wfi_out[4];
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/* CPU Power status towards INTC Redirect. */
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qemu_irq cpu_power_status[4];
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qemu_irq irq_imr;
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uint8_t cpu_pwrdwn_req;
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uint8_t cpu_in_wfi;
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RegisterInfoArray *reg_array;
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uint32_t regs[APU_R_MAX];
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RegisterInfo regs_info[APU_R_MAX];
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};
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#endif
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