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Throw RI for invalid MFMC0-class instructions. Introduce optional 

MIPS_STRICT_STANDARD define to adhere more to the spec than it makes
sense in normal operation.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2650 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-04-11 02:24:14 +00:00
parent 2423f6601a
commit b48cfdffd9
2 changed files with 18 additions and 3 deletions
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5
target-mips/mips-defs.h
View File

@ -19,4 +19,9 @@
#define TARGET_LONG_BITS 32
#endif
/* Strictly follow the architecture standard: Disallow "special"
instruction handling for PMON/SPIM, force cycle-dependent
Count/Compare maintenance. */
//#define MIPS_STRICT_STANDARD 1
#endif /* !defined (__QEMU_MIPS_DEFS_H__) */

16
target-mips/translate.c
View File

@ -305,7 +305,7 @@ enum {
};
/* MFMC0 opcodes */
#define MASK_MFMC0(op) MASK_CP0(op) | (op & ((0x0C << 11) | (1 << 5)))
#define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
enum {
OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
@ -4715,8 +4715,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
case OPC_MTLO: /* Move to HI/LO */
gen_HILO(ctx, op1, rs);
break;
case OPC_PMON: /* Pmon entry point */
case OPC_PMON: /* Pmon entry point, also R4010 selsl */
#ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("PMON / selsl");
generate_exception(ctx, EXCP_RI);
#else
gen_op_pmon(sa);
#endif
break;
case OPC_SYSCALL:
generate_exception(ctx, EXCP_SYSCALL);
@ -4724,10 +4729,15 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
case OPC_BREAK:
generate_exception(ctx, EXCP_BREAK);
break;
case OPC_SPIM: /* SPIM ? */
case OPC_SPIM:
#ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("SPIM");
generate_exception(ctx, EXCP_RI);
#else
/* Implemented as RI exception for now. */
MIPS_INVAL("spim (unofficial)");
generate_exception(ctx, EXCP_RI);
#endif
break;
case OPC_SYNC:
/* Treat as a noop. */