hw/arm: Fix some typos in comments (most found by codespell)
Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230409200526.1156456-1-sw@weilnetz.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -126,7 +126,7 @@ config OLIMEX_STM32_H405
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config NSERIES
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bool
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select OMAP
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select TMP105 # tempature sensor
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select TMP105 # temperature sensor
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select BLIZZARD # LCD/TV controller
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select ONENAND
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select TSC210X # touchscreen/sensors/audio
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@ -326,7 +326,7 @@ static int mapline_size(const int *mapline)
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/*
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* Initialize board IRQs.
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* These IRQs contain splitted Int/External Combiner and External Gic IRQs.
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* These IRQs contain split Int/External Combiner and External Gic IRQs.
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*/
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static void exynos4210_init_board_irqs(Exynos4210State *s)
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{
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@ -744,7 +744,7 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
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* - SDMA
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* - ADMA2
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*
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* As this part of the Exynos4210 is not publically available,
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* As this part of the Exynos4210 is not publicly available,
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* we used the "HS-MMC Controller S3C2416X RISC Microprocessor"
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* public datasheet which is very similar (implementing
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* MMC Specification Version 4.0 being the only difference noted)
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@ -100,7 +100,7 @@
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#define MP_LCD_SPI_CMD 0x00104011
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#define MP_LCD_SPI_INVALID 0x00000000
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/* Commmands */
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/* Commands */
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#define MP_LCD_INST_SETPAGE0 0xB0
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/* ... */
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#define MP_LCD_INST_SETPAGE7 0xB7
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@ -4057,7 +4057,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
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s->led[1] = omap_lpg_init(system_memory,
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0xfffbd800, omap_findclk(s, "clk32-kHz"));
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/* Register mappings not currenlty implemented:
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/* Register mappings not currently implemented:
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* MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
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* MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
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* USB W2FC fffb4000 - fffb47ff
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@ -2523,7 +2523,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
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omap_findclk(s, "func_96m_clk"),
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omap_findclk(s, "core_l4_iclk"));
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/* All register mappings (includin those not currenlty implemented):
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/* All register mappings (including those not currently implemented):
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* SystemControlMod 48000000 - 48000fff
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* SystemControlL4 48001000 - 48001fff
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* 32kHz Timer Mod 48004000 - 48004fff
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@ -694,7 +694,7 @@ static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size)
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build_append_int_noprefix(table_data, 0xE, 1); /* Type */
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build_append_int_noprefix(table_data, 16, 1); /* Length */
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build_append_int_noprefix(table_data, 0, 2); /* Reserved */
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/* Discovery Range Base Addres */
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/* Discovery Range Base Address */
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build_append_int_noprefix(table_data, base, 8);
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build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */
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}
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@ -2052,7 +2052,7 @@ static void machvirt_init(MachineState *machine)
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int pa_bits;
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/*
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* Instanciate a temporary CPU object to find out about what
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* Instantiate a temporary CPU object to find out about what
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* we are about to deal with. Once this is done, get rid of
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* the object.
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*/
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@ -659,7 +659,7 @@ static void versal_virt_init(MachineState *machine)
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fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
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/* Make the APU cpu address space visible to virtio and other
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* modules unaware of muliple address-spaces. */
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* modules unaware of multiple address-spaces. */
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memory_region_add_subregion_overlap(get_system_memory(),
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0, &s->soc.fpd.apu.mr, 0);
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