pci: make pci_bar() aware of header type 1.
make pci_bar() aware of header type 1. When PCI_ROM_SLOT it should return PCI_ROM_ADDRESS1 (!= PCI_ROM_ADDRESS) Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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5029fe12dc
commit
b3b1169731
18
hw/pci.c
18
hw/pci.c
@ -84,9 +84,15 @@ static const VMStateDescription vmstate_pcibus = {
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}
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}
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};
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};
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static inline int pci_bar(int reg)
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static int pci_bar(PCIDevice *d, int reg)
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{
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{
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return reg == PCI_ROM_SLOT ? PCI_ROM_ADDRESS : PCI_BASE_ADDRESS_0 + reg * 4;
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uint8_t type;
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if (reg != PCI_ROM_SLOT)
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return PCI_BASE_ADDRESS_0 + reg * 4;
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type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
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return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
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}
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}
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static void pci_device_reset(PCIDevice *dev)
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static void pci_device_reset(PCIDevice *dev)
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@ -102,7 +108,7 @@ static void pci_device_reset(PCIDevice *dev)
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if (!dev->io_regions[r].size) {
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if (!dev->io_regions[r].size) {
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continue;
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continue;
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}
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}
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pci_set_long(dev->config + pci_bar(r), dev->io_regions[r].type);
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pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
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}
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}
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pci_update_mappings(dev);
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pci_update_mappings(dev);
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}
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}
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@ -472,7 +478,7 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
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r->map_func = map_func;
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r->map_func = map_func;
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wmask = ~(size - 1);
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wmask = ~(size - 1);
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addr = pci_bar(region_num);
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addr = pci_bar(pci_dev, region_num);
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if (region_num == PCI_ROM_SLOT) {
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if (region_num == PCI_ROM_SLOT) {
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/* ROM enable bit is writeable */
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/* ROM enable bit is writeable */
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wmask |= PCI_ROM_ADDRESS_ENABLE;
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wmask |= PCI_ROM_ADDRESS_ENABLE;
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@ -494,7 +500,7 @@ static void pci_update_mappings(PCIDevice *d)
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if (r->size != 0) {
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if (r->size != 0) {
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if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
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if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
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if (cmd & PCI_COMMAND_IO) {
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if (cmd & PCI_COMMAND_IO) {
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new_addr = pci_get_long(d->config + pci_bar(i));
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new_addr = pci_get_long(d->config + pci_bar(d, i));
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new_addr = new_addr & ~(r->size - 1);
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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last_addr = new_addr + r->size - 1;
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/* NOTE: we have only 64K ioports on PC */
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/* NOTE: we have only 64K ioports on PC */
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@ -507,7 +513,7 @@ static void pci_update_mappings(PCIDevice *d)
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}
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}
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} else {
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} else {
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if (cmd & PCI_COMMAND_MEMORY) {
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if (cmd & PCI_COMMAND_MEMORY) {
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new_addr = pci_get_long(d->config + pci_bar(i));
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new_addr = pci_get_long(d->config + pci_bar(d, i));
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/* the ROM slot has a specific enable bit */
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/* the ROM slot has a specific enable bit */
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if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE))
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if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE))
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goto no_mem_map;
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goto no_mem_map;
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1
hw/pci.h
1
hw/pci.h
@ -120,6 +120,7 @@ typedef struct PCIIORegion {
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#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
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#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
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#define PCI_ROM_ADDRESS_ENABLE 0x01
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#define PCI_ROM_ADDRESS_ENABLE 0x01
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#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
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#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
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#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
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#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
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#define PCI_MIN_GNT 0x3e /* 8 bits */
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#define PCI_MIN_GNT 0x3e /* 8 bits */
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