target-ppc: add cnttzw[.] instruction
Add ISA3.0: Count trailing zeros word instruction. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -38,6 +38,7 @@ DEF_HELPER_4(divweu, tl, env, tl, tl, i32)
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DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
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DEF_HELPER_FLAGS_1(cntlzw, TCG_CALL_NO_RWG_SE, tl, tl)
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DEF_HELPER_FLAGS_1(cnttzw, TCG_CALL_NO_RWG_SE, tl, tl)
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DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
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DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
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DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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@ -145,6 +145,11 @@ target_ulong helper_cntlzw(target_ulong t)
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return clz32(t);
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}
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target_ulong helper_cnttzw(target_ulong t)
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{
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return ctz32(t);
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}
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#if defined(TARGET_PPC64)
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target_ulong helper_cntlzd(target_ulong t)
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{
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@ -1583,6 +1583,16 @@ static void gen_cntlzw(DisasContext *ctx)
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if (unlikely(Rc(ctx->opcode) != 0))
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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}
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/* cnttzw */
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static void gen_cnttzw(DisasContext *ctx)
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{
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gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
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if (unlikely(Rc(ctx->opcode) != 0)) {
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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}
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}
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/* eqv & eqv. */
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GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
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/* extsb & extsb. */
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@ -10057,6 +10067,7 @@ GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
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GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
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GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
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GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
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GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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