target/arm: PMU: Add instruction and cycle events
The instruction event is only enabled when icount is used, cycles are always supported. Always defining get_cycle_count (but altering its behavior depending on CONFIG_USER_ONLY) allows us to remove some CONFIG_USER_ONLY #defines throughout the rest of the code. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-12-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Aaron Lindsay
Peter Maydell
parent
5ecdd3e47c
commit
b2e2372511
@ -15,6 +15,7 @@
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#include "arm_ldst.h"
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#include <zlib.h> /* For crc32 */
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#include "exec/semihost.h"
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#include "sysemu/cpus.h"
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#include "sysemu/kvm.h"
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#include "fpu/softfloat.h"
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#include "qemu/range.h"
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@ -1021,7 +1022,48 @@ typedef struct pm_event {
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uint64_t (*get_count)(CPUARMState *);
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} pm_event;
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static bool event_always_supported(CPUARMState *env)
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{
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return true;
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}
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/*
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* Return the underlying cycle count for the PMU cycle counters. If we're in
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* usermode, simply return 0.
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*/
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static uint64_t cycles_get_count(CPUARMState *env)
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{
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#ifndef CONFIG_USER_ONLY
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return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
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ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
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#else
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return cpu_get_host_ticks();
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#endif
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}
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#ifndef CONFIG_USER_ONLY
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static bool instructions_supported(CPUARMState *env)
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{
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return use_icount == 1 /* Precise instruction counting */;
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}
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static uint64_t instructions_get_count(CPUARMState *env)
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{
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return (uint64_t)cpu_get_icount_raw();
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}
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#endif
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static const pm_event pm_events[] = {
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#ifndef CONFIG_USER_ONLY
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{ .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */
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.supported = instructions_supported,
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.get_count = instructions_get_count,
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},
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{ .number = 0x011, /* CPU_CYCLES, Cycle */
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.supported = event_always_supported,
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.get_count = cycles_get_count,
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}
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#endif
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};
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/*
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@ -1030,7 +1072,7 @@ static const pm_event pm_events[] = {
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* should first be updated to something sparse instead of the current
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* supported_event_map[] array.
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*/
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#define MAX_EVENT_ID 0x0
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#define MAX_EVENT_ID 0x11
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#define UNSUPPORTED_EVENT UINT16_MAX
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static uint16_t supported_event_map[MAX_EVENT_ID + 1];
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@ -1131,8 +1173,6 @@ static CPAccessResult pmreg_access_swinc(CPUARMState *env,
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return pmreg_access(env, ri, isread);
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}
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#ifndef CONFIG_USER_ONLY
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static CPAccessResult pmreg_access_selr(CPUARMState *env,
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const ARMCPRegInfo *ri,
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bool isread)
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@ -1243,9 +1283,7 @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
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*/
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void pmccntr_op_start(CPUARMState *env)
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{
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uint64_t cycles = 0;
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cycles = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
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ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
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uint64_t cycles = cycles_get_count(env);
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if (pmu_counter_enabled(env, 31)) {
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uint64_t eff_cycles = cycles;
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@ -1391,42 +1429,6 @@ static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
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pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
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}
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#else /* CONFIG_USER_ONLY */
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void pmccntr_op_start(CPUARMState *env)
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{
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}
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void pmccntr_op_finish(CPUARMState *env)
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{
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}
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void pmevcntr_op_start(CPUARMState *env, uint8_t i)
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{
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}
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void pmevcntr_op_finish(CPUARMState *env, uint8_t i)
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{
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}
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void pmu_op_start(CPUARMState *env)
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{
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}
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void pmu_op_finish(CPUARMState *env)
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{
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}
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void pmu_pre_el_change(ARMCPU *cpu, void *ignored)
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{
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}
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void pmu_post_el_change(ARMCPU *cpu, void *ignored)
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{
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}
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#endif
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static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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@ -1823,7 +1825,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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/* Unimplemented so WI. */
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{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
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.access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP },
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#ifndef CONFIG_USER_ONLY
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{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
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.access = PL0_RW, .type = ARM_CP_ALIAS,
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.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
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@ -1845,7 +1846,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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.fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
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.readfn = pmccntr_read, .writefn = pmccntr_write,
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.raw_readfn = raw_read, .raw_writefn = raw_write, },
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#endif
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{ .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7,
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.writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32,
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.access = PL0_RW, .accessfn = pmreg_access,
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@ -5675,7 +5675,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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* count register.
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*/
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unsigned int i, pmcrn = 0;
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#ifndef CONFIG_USER_ONLY
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ARMCPRegInfo pmcr = {
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.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
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.access = PL0_RW,
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@ -5732,7 +5731,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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g_free(pmevtyper_name);
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g_free(pmevtyper_el0_name);
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}
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#endif
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ARMCPRegInfo clidr = {
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.name = "CLIDR", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
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