Hexagon (target/hexagon/arch.[ch]) utility functions
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-16-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Taylor Simpson
Richard Henderson
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target/hexagon/arch.c
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300
target/hexagon/arch.c
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/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "fpu/softfloat.h"
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#include "cpu.h"
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#include "fma_emu.h"
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#include "arch.h"
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#include "macros.h"
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#define SF_BIAS 127
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#define SF_MAXEXP 254
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#define SF_MANTBITS 23
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#define float32_nan make_float32(0xffffffff)
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#define BITS_MASK_8 0x5555555555555555ULL
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#define PAIR_MASK_8 0x3333333333333333ULL
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#define NYBL_MASK_8 0x0f0f0f0f0f0f0f0fULL
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#define BYTE_MASK_8 0x00ff00ff00ff00ffULL
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#define HALF_MASK_8 0x0000ffff0000ffffULL
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#define WORD_MASK_8 0x00000000ffffffffULL
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uint64_t interleave(uint32_t odd, uint32_t even)
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{
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/* Convert to long long */
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uint64_t myodd = odd;
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uint64_t myeven = even;
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/* First, spread bits out */
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myodd = (myodd | (myodd << 16)) & HALF_MASK_8;
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myeven = (myeven | (myeven << 16)) & HALF_MASK_8;
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myodd = (myodd | (myodd << 8)) & BYTE_MASK_8;
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myeven = (myeven | (myeven << 8)) & BYTE_MASK_8;
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myodd = (myodd | (myodd << 4)) & NYBL_MASK_8;
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myeven = (myeven | (myeven << 4)) & NYBL_MASK_8;
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myodd = (myodd | (myodd << 2)) & PAIR_MASK_8;
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myeven = (myeven | (myeven << 2)) & PAIR_MASK_8;
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myodd = (myodd | (myodd << 1)) & BITS_MASK_8;
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myeven = (myeven | (myeven << 1)) & BITS_MASK_8;
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/* Now OR together */
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return myeven | (myodd << 1);
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}
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uint64_t deinterleave(uint64_t src)
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{
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/* Get odd and even bits */
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uint64_t myodd = ((src >> 1) & BITS_MASK_8);
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uint64_t myeven = (src & BITS_MASK_8);
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/* Unspread bits */
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myeven = (myeven | (myeven >> 1)) & PAIR_MASK_8;
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myodd = (myodd | (myodd >> 1)) & PAIR_MASK_8;
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myeven = (myeven | (myeven >> 2)) & NYBL_MASK_8;
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myodd = (myodd | (myodd >> 2)) & NYBL_MASK_8;
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myeven = (myeven | (myeven >> 4)) & BYTE_MASK_8;
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myodd = (myodd | (myodd >> 4)) & BYTE_MASK_8;
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myeven = (myeven | (myeven >> 8)) & HALF_MASK_8;
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myodd = (myodd | (myodd >> 8)) & HALF_MASK_8;
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myeven = (myeven | (myeven >> 16)) & WORD_MASK_8;
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myodd = (myodd | (myodd >> 16)) & WORD_MASK_8;
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/* Return odd bits in upper half */
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return myeven | (myodd << 32);
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}
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uint32_t carry_from_add64(uint64_t a, uint64_t b, uint32_t c)
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{
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uint64_t tmpa, tmpb, tmpc;
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tmpa = fGETUWORD(0, a);
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tmpb = fGETUWORD(0, b);
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tmpc = tmpa + tmpb + c;
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tmpa = fGETUWORD(1, a);
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tmpb = fGETUWORD(1, b);
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tmpc = tmpa + tmpb + fGETUWORD(1, tmpc);
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tmpc = fGETUWORD(1, tmpc);
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return tmpc;
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}
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int32_t conv_round(int32_t a, int n)
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{
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int64_t val;
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if (n == 0) {
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val = a;
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} else if ((a & ((1 << (n - 1)) - 1)) == 0) { /* N-1..0 all zero? */
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/* Add LSB from int part */
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val = ((fSE32_64(a)) + (int64_t) (((uint32_t) ((1 << n) & a)) >> 1));
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} else {
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val = ((fSE32_64(a)) + (1 << (n - 1)));
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}
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val = val >> n;
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return (int32_t)val;
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}
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/* Floating Point Stuff */
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static const int softfloat_roundingmodes[] = {
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float_round_nearest_even,
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float_round_to_zero,
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float_round_down,
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float_round_up,
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};
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void arch_fpop_start(CPUHexagonState *env)
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{
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set_float_exception_flags(0, &env->fp_status);
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set_float_rounding_mode(
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softfloat_roundingmodes[fREAD_REG_FIELD(USR, USR_FPRND)],
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&env->fp_status);
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}
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#ifdef CONFIG_USER_ONLY
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/*
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* Hexagon Linux kernel only sets the relevant bits in USR (user status
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* register). The exception isn't raised to user mode, so we don't
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* model it in qemu user mode.
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*/
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#define RAISE_FP_EXCEPTION do {} while (0)
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#endif
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#define SOFTFLOAT_TEST_FLAG(FLAG, MYF, MYE) \
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do { \
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if (flags & FLAG) { \
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if (GET_USR_FIELD(USR_##MYF) == 0) { \
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SET_USR_FIELD(USR_##MYF, 1); \
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if (GET_USR_FIELD(USR_##MYE)) { \
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RAISE_FP_EXCEPTION; \
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} \
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} \
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} \
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} while (0)
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void arch_fpop_end(CPUHexagonState *env)
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{
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int flags = get_float_exception_flags(&env->fp_status);
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if (flags != 0) {
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SOFTFLOAT_TEST_FLAG(float_flag_inexact, FPINPF, FPINPE);
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SOFTFLOAT_TEST_FLAG(float_flag_divbyzero, FPDBZF, FPDBZE);
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SOFTFLOAT_TEST_FLAG(float_flag_invalid, FPINVF, FPINVE);
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SOFTFLOAT_TEST_FLAG(float_flag_overflow, FPOVFF, FPOVFE);
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SOFTFLOAT_TEST_FLAG(float_flag_underflow, FPUNFF, FPUNFE);
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}
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}
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static float32 float32_mul_pow2(float32 a, uint32_t p, float_status *fp_status)
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{
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float32 b = make_float32((SF_BIAS + p) << SF_MANTBITS);
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return float32_mul(a, b, fp_status);
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}
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int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjust,
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float_status *fp_status)
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{
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int n_exp;
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int d_exp;
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int ret = 0;
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float32 RsV, RtV, RdV;
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int PeV = 0;
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RsV = *Rs;
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RtV = *Rt;
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if (float32_is_any_nan(RsV) && float32_is_any_nan(RtV)) {
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if (extract32(RsV & RtV, 22, 1) == 0) {
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float_raise(float_flag_invalid, fp_status);
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}
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RdV = RsV = RtV = float32_nan;
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} else if (float32_is_any_nan(RsV)) {
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if (extract32(RsV, 22, 1) == 0) {
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float_raise(float_flag_invalid, fp_status);
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}
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RdV = RsV = RtV = float32_nan;
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} else if (float32_is_any_nan(RtV)) {
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/* or put NaN in num/den fixup? */
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if (extract32(RtV, 22, 1) == 0) {
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float_raise(float_flag_invalid, fp_status);
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}
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RdV = RsV = RtV = float32_nan;
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} else if (float32_is_infinity(RsV) && float32_is_infinity(RtV)) {
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/* or put Inf in num fixup? */
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RdV = RsV = RtV = float32_nan;
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float_raise(float_flag_invalid, fp_status);
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} else if (float32_is_zero(RsV) && float32_is_zero(RtV)) {
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/* or put zero in num fixup? */
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RdV = RsV = RtV = float32_nan;
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float_raise(float_flag_invalid, fp_status);
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} else if (float32_is_zero(RtV)) {
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/* or put Inf in num fixup? */
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uint8_t RsV_sign = float32_is_neg(RsV);
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uint8_t RtV_sign = float32_is_neg(RtV);
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RsV = infinite_float32(RsV_sign ^ RtV_sign);
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RtV = float32_one;
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RdV = float32_one;
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if (float32_is_infinity(RsV)) {
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float_raise(float_flag_divbyzero, fp_status);
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}
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} else if (float32_is_infinity(RtV)) {
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RsV = make_float32(0x80000000 & (RsV ^ RtV));
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RtV = float32_one;
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RdV = float32_one;
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} else if (float32_is_zero(RsV)) {
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/* Does this just work itself out? */
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/* No, 0/Inf causes problems. */
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RsV = make_float32(0x80000000 & (RsV ^ RtV));
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RtV = float32_one;
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RdV = float32_one;
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} else if (float32_is_infinity(RsV)) {
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uint8_t RsV_sign = float32_is_neg(RsV);
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uint8_t RtV_sign = float32_is_neg(RtV);
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RsV = infinite_float32(RsV_sign ^ RtV_sign);
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RtV = float32_one;
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RdV = float32_one;
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} else {
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PeV = 0x00;
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/* Basic checks passed */
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n_exp = float32_getexp(RsV);
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d_exp = float32_getexp(RtV);
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if ((n_exp - d_exp + SF_BIAS) <= SF_MANTBITS) {
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/* Near quotient underflow / inexact Q */
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PeV = 0x80;
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RtV = float32_mul_pow2(RtV, -64, fp_status);
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RsV = float32_mul_pow2(RsV, 64, fp_status);
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} else if ((n_exp - d_exp + SF_BIAS) > (SF_MAXEXP - 24)) {
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/* Near quotient overflow */
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PeV = 0x40;
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RtV = float32_mul_pow2(RtV, 32, fp_status);
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RsV = float32_mul_pow2(RsV, -32, fp_status);
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} else if (n_exp <= SF_MANTBITS + 2) {
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RtV = float32_mul_pow2(RtV, 64, fp_status);
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RsV = float32_mul_pow2(RsV, 64, fp_status);
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} else if (d_exp <= 1) {
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RtV = float32_mul_pow2(RtV, 32, fp_status);
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RsV = float32_mul_pow2(RsV, 32, fp_status);
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} else if (d_exp > 252) {
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RtV = float32_mul_pow2(RtV, -32, fp_status);
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RsV = float32_mul_pow2(RsV, -32, fp_status);
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}
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RdV = 0;
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ret = 1;
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}
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*Rs = RsV;
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*Rt = RtV;
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*Rd = RdV;
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*adjust = PeV;
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return ret;
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}
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int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust,
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float_status *fp_status)
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{
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float32 RsV, RdV;
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int PeV = 0;
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int r_exp;
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int ret = 0;
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RsV = *Rs;
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if (float32_is_infinity(RsV)) {
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if (extract32(RsV, 22, 1) == 0) {
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float_raise(float_flag_invalid, fp_status);
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}
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RdV = RsV = float32_nan;
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} else if (float32_lt(RsV, float32_zero, fp_status)) {
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/* Negative nonzero values are NaN */
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float_raise(float_flag_invalid, fp_status);
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RsV = float32_nan;
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RdV = float32_nan;
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} else if (float32_is_infinity(RsV)) {
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/* or put Inf in num fixup? */
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RsV = infinite_float32(1);
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RdV = infinite_float32(1);
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} else if (float32_is_zero(RsV)) {
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/* or put zero in num fixup? */
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RdV = float32_one;
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} else {
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PeV = 0x00;
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/* Basic checks passed */
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r_exp = float32_getexp(RsV);
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if (r_exp <= 24) {
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RsV = float32_mul_pow2(RsV, 64, fp_status);
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PeV = 0xe0;
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}
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RdV = 0;
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ret = 1;
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}
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*Rs = RsV;
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*Rd = RdV;
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*adjust = PeV;
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return ret;
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}
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34
target/hexagon/arch.h
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34
target/hexagon/arch.h
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@ -0,0 +1,34 @@
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/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HEXAGON_ARCH_H
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#define HEXAGON_ARCH_H
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#include "qemu/int128.h"
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uint64_t interleave(uint32_t odd, uint32_t even);
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uint64_t deinterleave(uint64_t src);
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uint32_t carry_from_add64(uint64_t a, uint64_t b, uint32_t c);
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int32_t conv_round(int32_t a, int n);
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void arch_fpop_start(CPUHexagonState *env);
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void arch_fpop_end(CPUHexagonState *env);
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int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd,
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int *adjust, float_status *fp_status);
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int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust,
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float_status *fp_status);
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#endif
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