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s390x/tcg: Implement VECTOR ADD

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Introduce two types of fancy new helpers that will be reused a couple of
times

1. gen_gvec_fn_3: Call an existing tcg_gen_gvec_X function with 3
   parameters, simplifying parameter passing
2. gen_gvec128_3_i64: Call a function that performs 128 bit calculations
   using two 64 bit values per vector.

Luckily, for VECTOR ADD we already have everything we need.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
This commit is contained in:
David Hildenbrand 2019-04-10 23:08:40 +02:00
parent 85fa94e169
commit b1e67c8f23
2 changed files with 57 additions and 0 deletions
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5
target/s390x/insn-data.def
View File

@ -1054,6 +1054,11 @@
/* VECTOR UNPACK LOGICAL LOW */
F(0xe7d4, VUPLL, VRR_a, V, 0, 0, 0, 0, vup, 0, IF_VEC)
/* === Vector Integer Instructions === */
/* VECTOR ADD */
F(0xe7f3, VA, VRR_c, V, 0, 0, 0, 0, va, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
E(0xb250, CSP, RRE, Z, r1_32u, ra2, r1_P, 0, csp, 0, MO_TEUL, IF_PRIV)

52
target/s390x/translate_vx.inc.c
View File

@ -157,6 +157,41 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
16)
#define gen_gvec_dup64i(v1, c) \
tcg_gen_gvec_dup64i(vec_full_reg_offset(v1), 16, 16, c)
#define gen_gvec_fn_3(fn, es, v1, v2, v3) \
tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16)
/*
* Helper to carry out a 128 bit vector computation using 2 i64 values per
* vector.
*/
typedef void (*gen_gvec128_3_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn fn, uint8_t d, uint8_t a,
uint8_t b)
{
TCGv_i64 dh = tcg_temp_new_i64();
TCGv_i64 dl = tcg_temp_new_i64();
TCGv_i64 ah = tcg_temp_new_i64();
TCGv_i64 al = tcg_temp_new_i64();
TCGv_i64 bh = tcg_temp_new_i64();
TCGv_i64 bl = tcg_temp_new_i64();
read_vec_element_i64(ah, a, 0, ES_64);
read_vec_element_i64(al, a, 1, ES_64);
read_vec_element_i64(bh, b, 0, ES_64);
read_vec_element_i64(bl, b, 1, ES_64);
fn(dl, dh, al, ah, bl, bh);
write_vec_element_i64(dh, d, 0, ES_64);
write_vec_element_i64(dl, d, 1, ES_64);
tcg_temp_free_i64(dh);
tcg_temp_free_i64(dl);
tcg_temp_free_i64(ah);
tcg_temp_free_i64(al);
tcg_temp_free_i64(bh);
tcg_temp_free_i64(bl);
}
static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c)
{
@ -933,3 +968,20 @@ static DisasJumpType op_vup(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
static DisasJumpType op_va(DisasContext *s, DisasOps *o)
{
const uint8_t es = get_field(s->fields, m4);
if (es > ES_128) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
} else if (es == ES_128) {
gen_gvec128_3_i64(tcg_gen_add2_i64, get_field(s->fields, v1),
get_field(s->fields, v2), get_field(s->fields, v3));
return DISAS_NEXT;
}
gen_gvec_fn_3(add, es, get_field(s->fields, v1), get_field(s->fields, v2),
get_field(s->fields, v3));
return DISAS_NEXT;
}