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Fix mips semihosting regression.

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Merge tag 'pull-semi-20220802' of https://gitlab.com/rth7680/qemu into staging

Fix mips semihosting regression.

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# gpg: Signature made Tue 02 Aug 2022 05:57:21 PM PDT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-semi-20220802' of https://gitlab.com/rth7680/qemu:
  target/mips: Advance pc after semihosting exception

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-08-02 17:59:36 -07:00
commit b15bd4532f
6 changed files with 16 additions and 11 deletions
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6
target/mips/tcg/micromips_translate.c.inc
View File

@ -826,7 +826,7 @@ static void gen_pool16c_insn(DisasContext *ctx)
break;
case SDBBP16:
if (is_uhi(extract32(ctx->opcode, 0, 4))) {
generate_exception_end(ctx, EXCP_SEMIHOST);
ctx->base.is_jmp = DISAS_SEMIHOST;
} else {
/*
* XXX: not clear which exception should be raised
@ -942,7 +942,7 @@ static void gen_pool16c_r6_insn(DisasContext *ctx)
case R6_SDBBP16:
/* SDBBP16 */
if (is_uhi(extract32(ctx->opcode, 6, 4))) {
generate_exception_end(ctx, EXCP_SEMIHOST);
ctx->base.is_jmp = DISAS_SEMIHOST;
} else {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
generate_exception(ctx, EXCP_RI);
@ -1311,7 +1311,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
break;
case SDBBP:
if (is_uhi(extract32(ctx->opcode, 16, 10))) {
generate_exception_end(ctx, EXCP_SEMIHOST);
ctx->base.is_jmp = DISAS_SEMIHOST;
} else {
check_insn(ctx, ISA_MIPS_R1);
if (ctx->hflags & MIPS_HFLAG_SBRI) {

2
target/mips/tcg/mips16e_translate.c.inc
View File

@ -952,7 +952,7 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
break;
case RR_SDBBP:
if (is_uhi(extract32(ctx->opcode, 5, 6))) {
generate_exception_end(ctx, EXCP_SEMIHOST);
ctx->base.is_jmp = DISAS_SEMIHOST;
} else {
/*
* XXX: not clear which exception should be raised

4
target/mips/tcg/nanomips_translate.c.inc
View File

@ -3695,7 +3695,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case NM_SDBBP:
if (is_uhi(extract32(ctx->opcode, 0, 19))) {
generate_exception_end(ctx, EXCP_SEMIHOST);
ctx->base.is_jmp = DISAS_SEMIHOST;
} else {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
gen_reserved_instruction(ctx);
@ -4634,7 +4634,7 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
break;
case NM_SDBBP16:
if (is_uhi(extract32(ctx->opcode, 0, 3))) {
generate_exception_end(ctx, EXCP_SEMIHOST);
ctx->base.is_jmp = DISAS_SEMIHOST;
} else {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
gen_reserved_instruction(ctx);

1
target/mips/tcg/sysemu/tlb_helper.c
View File

@ -1056,6 +1056,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
case EXCP_SEMIHOST:
cs->exception_index = EXCP_NONE;
mips_semihosting(env);
env->active_tc.PC += env->error_code;
return;
case EXCP_DSS:
env->CP0_Debug |= 1 << CP0DB_DSS;

10
target/mips/tcg/translate.c
View File

@ -1213,9 +1213,6 @@ TCGv_i64 fpu_f64[32];
#include "exec/gen-icount.h"
#define DISAS_STOP DISAS_TARGET_0
#define DISAS_EXIT DISAS_TARGET_1
static const char regnames_HI[][4] = {
"HI0", "HI1", "HI2", "HI3",
};
@ -13902,7 +13899,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
break;
case R6_OPC_SDBBP:
if (is_uhi(extract32(ctx->opcode, 6, 20))) {
generate_exception_end(ctx, EXCP_SEMIHOST);
ctx->base.is_jmp = DISAS_SEMIHOST;
} else {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
gen_reserved_instruction(ctx);
@ -14314,7 +14311,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SDBBP:
if (is_uhi(extract32(ctx->opcode, 6, 20))) {
generate_exception_end(ctx, EXCP_SEMIHOST);
ctx->base.is_jmp = DISAS_SEMIHOST;
} else {
/*
* XXX: not clear which exception should be raised
@ -16098,6 +16095,9 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
if (is_slot) {
gen_branch(ctx, insn_bytes);
}
if (ctx->base.is_jmp == DISAS_SEMIHOST) {
generate_exception_err(ctx, EXCP_SEMIHOST, insn_bytes);
}
ctx->base.pc_next += insn_bytes;
if (ctx->base.is_jmp != DISAS_NEXT) {

4
target/mips/tcg/translate.h
View File

@ -51,6 +51,10 @@ typedef struct DisasContext {
int gi;
} DisasContext;
#define DISAS_STOP DISAS_TARGET_0
#define DISAS_EXIT DISAS_TARGET_1
#define DISAS_SEMIHOST DISAS_TARGET_2
/* MIPS major opcodes */
#define MASK_OP_MAJOR(op) (op & (0x3F << 26))