Implement UA2005 hypervisor traps
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5327 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -38,8 +38,6 @@ DEF_HELPER(void, helper_tick_set_count, (void *opaque, uint64_t count))
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DEF_HELPER(uint64_t, helper_tick_get_count, (void *opaque))
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DEF_HELPER(void, helper_tick_set_limit, (void *opaque, uint64_t limit))
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#endif
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DEF_HELPER(void, helper_trap, (target_ulong nb_trap))
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DEF_HELPER(void, helper_trapcc, (target_ulong nb_trap, target_ulong do_trap))
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DEF_HELPER(void, helper_check_align, (target_ulong addr, uint32_t align))
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DEF_HELPER(void, helper_debug, (void))
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DEF_HELPER(void, helper_save, (void))
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@ -55,20 +55,6 @@ void raise_exception(int tt)
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cpu_loop_exit();
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}
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void helper_trap(target_ulong nb_trap)
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{
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env->exception_index = TT_TRAP + (nb_trap & 0x7f);
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cpu_loop_exit();
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}
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void helper_trapcc(target_ulong nb_trap, target_ulong do_trap)
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{
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if (do_trap) {
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env->exception_index = TT_TRAP + (nb_trap & 0x7f);
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cpu_loop_exit();
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}
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}
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static inline void set_cwp(int new_cwp)
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{
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cpu_set_cwp(env, new_cwp);
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@ -93,6 +93,9 @@ typedef struct DisasContext {
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#define QFPREG(r) (r & 0x1c)
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#endif
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#define UA2005_HTRAP_MASK 0xff
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#define V8_TRAP_MASK 0x7f
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static int sign_extend(int x, int len)
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{
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len = 32 - len;
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@ -2019,9 +2022,16 @@ static void disas_sparc_insn(DisasContext * dc)
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cond = GET_FIELD(insn, 3, 6);
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if (cond == 0x8) {
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save_state(dc, cpu_cond);
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tcg_gen_helper_0_1(helper_trap, cpu_dst);
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if ((dc->def->features & CPU_FEATURE_HYPV) &&
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supervisor(dc))
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tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK);
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else
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tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK);
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tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP);
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tcg_gen_helper_0_1(raise_exception, cpu_dst);
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} else if (cond != 0) {
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TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
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int l1;
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#ifdef TARGET_SPARC64
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/* V9 icc/xcc */
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int cc = GET_FIELD_SP(insn, 11, 12);
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@ -2037,7 +2047,18 @@ static void disas_sparc_insn(DisasContext * dc)
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save_state(dc, cpu_cond);
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gen_cond(r_cond, 0, cond);
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#endif
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tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
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l1 = gen_new_label();
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tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
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if ((dc->def->features & CPU_FEATURE_HYPV) &&
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supervisor(dc))
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tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK);
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else
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tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK);
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tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP);
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tcg_gen_helper_0_1(raise_exception, cpu_dst);
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gen_set_label(l1);
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tcg_temp_free(r_cond);
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}
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gen_op_next_insn();
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