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target/arm: Fix SVE STR increment

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The previous change missed updating one of the increments and
one of the MemOps.  Add a test case for all vector lengths.

Cc: qemu-stable@nongnu.org
Fixes: e6dd5e782b ("target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231031143215.29764-1-richard.henderson@linaro.org
[PMM: fixed checkpatch nit]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-31 07:32:15 -07:00 committed by Peter Maydell
parent 854c001f12
commit b11293c212
3 changed files with 57 additions and 3 deletions
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5
target/arm/tcg/translate-sve.c
View File

@ -4294,7 +4294,7 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
t0 = tcg_temp_new_i64(); t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64(); t1 = tcg_temp_new_i64();
t16 = tcg_temp_new_i128(); t16 = tcg_temp_new_i128();
for (i = 0; i < len_align; i += 8) { for (i = 0; i < len_align; i += 16) {
tcg_gen_ld_i64(t0, base, vofs + i); tcg_gen_ld_i64(t0, base, vofs + i);
tcg_gen_ld_i64(t1, base, vofs + i + 8); tcg_gen_ld_i64(t1, base, vofs + i + 8);
tcg_gen_concat_i64_i128(t16, t0, t1); tcg_gen_concat_i64_i128(t16, t0, t1);
@ -4320,7 +4320,8 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
t16 = tcg_temp_new_i128(); t16 = tcg_temp_new_i128();
tcg_gen_concat_i64_i128(t16, t0, t1); tcg_gen_concat_i64_i128(t16, t0, t1);
tcg_gen_qemu_st_i128(t16, clean_addr, midx, MO_LEUQ); tcg_gen_qemu_st_i128(t16, clean_addr, midx,
MO_LE | MO_128 | MO_ATOM_NONE);
tcg_gen_addi_i64(clean_addr, clean_addr, 16); tcg_gen_addi_i64(clean_addr, clean_addr, 16);
tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop);

6
tests/tcg/aarch64/Makefile.target
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@ -103,7 +103,11 @@ sha512-sve: CFLAGS=-O3 -march=armv8.1-a+sve
sha512-sve: sha512.c sha512-sve: sha512.c
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
TESTS += sha512-sve sve-str: CFLAGS=-O1 -march=armv8.1-a+sve
sve-str: sve-str.c
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
TESTS += sha512-sve sve-str
ifneq ($(GDB),) ifneq ($(GDB),)
GDB_SCRIPT=$(SRC_PATH)/tests/guest-debug/run-test.py GDB_SCRIPT=$(SRC_PATH)/tests/guest-debug/run-test.py

49
tests/tcg/aarch64/sve-str.c Normal file
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@ -0,0 +1,49 @@
#include <stdio.h>
#include <sys/prctl.h>
#define N (256 + 16)
static int __attribute__((noinline)) test(int vl)
{
unsigned char buf[N];
int err = 0;
for (int i = 0; i < N; ++i) {
buf[i] = (unsigned char)i;
}
asm volatile (
"mov z0.b, #255\n\t"
"str z0, %0"
: : "m" (buf) : "z0", "memory");
for (int i = 0; i < vl; ++i) {
if (buf[i] != 0xff) {
fprintf(stderr, "vl %d, index %d, expected 255, got %d\n",
vl, i, buf[i]);
err = 1;
}
}
for (int i = vl; i < N; ++i) {
if (buf[i] != (unsigned char)i) {
fprintf(stderr, "vl %d, index %d, expected %d, got %d\n",
vl, i, (unsigned char)i, buf[i]);
err = 1;
}
}
return err;
}
int main()
{
int err = 0;
for (int i = 16; i <= 256; i += 16) {
if (prctl(PR_SVE_SET_VL, i, 0, 0, 0, 0) == i) {
err |= test(i);
}
}
return err;
}