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s390x/tcg: Implement VECTOR CHECKSUM

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Time to introduce read_vec_element_i32 and write_vec_element_i32.
Take proper care of properly adding the carry. We can perform both
additions including the carry via tcg_gen_add2_i32().

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
This commit is contained in:
David Hildenbrand 2019-03-20 23:18:59 +01:00
parent 801aa78bd0
commit b0160ec99a
2 changed files with 67 additions and 0 deletions
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2
target/s390x/insn-data.def
View File

@ -1072,6 +1072,8 @@
F(0xe7f2, VAVG, VRR_c, V, 0, 0, 0, 0, vavg, 0, IF_VEC) F(0xe7f2, VAVG, VRR_c, V, 0, 0, 0, 0, vavg, 0, IF_VEC)
/* VECTOR AVERAGE LOGICAL */ /* VECTOR AVERAGE LOGICAL */
F(0xe7f0, VAVGL, VRR_c, V, 0, 0, 0, 0, vavgl, 0, IF_VEC) F(0xe7f0, VAVGL, VRR_c, V, 0, 0, 0, 0, vavgl, 0, IF_VEC)
/* VECTOR CHECKSUM */
F(0xe766, VCKSM, VRR_c, V, 0, 0, 0, 0, vcksm, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */ /* COMPARE AND SWAP AND PURGE */

65
target/s390x/translate_vx.inc.c
View File

@ -90,6 +90,33 @@ static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,
} }
} }
static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr,
TCGMemOp memop)
{
const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
switch (memop) {
case ES_8:
tcg_gen_ld8u_i32(dst, cpu_env, offs);
break;
case ES_16:
tcg_gen_ld16u_i32(dst, cpu_env, offs);
break;
case ES_8 | MO_SIGN:
tcg_gen_ld8s_i32(dst, cpu_env, offs);
break;
case ES_16 | MO_SIGN:
tcg_gen_ld16s_i32(dst, cpu_env, offs);
break;
case ES_32:
case ES_32 | MO_SIGN:
tcg_gen_ld_i32(dst, cpu_env, offs);
break;
default:
g_assert_not_reached();
}
}
static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr, static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
TCGMemOp memop) TCGMemOp memop)
{ {
@ -113,6 +140,25 @@ static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
} }
} }
static void write_vec_element_i32(TCGv_i32 src, int reg, uint8_t enr,
TCGMemOp memop)
{
const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
switch (memop) {
case ES_8:
tcg_gen_st8_i32(src, cpu_env, offs);
break;
case ES_16:
tcg_gen_st16_i32(src, cpu_env, offs);
break;
case ES_32:
tcg_gen_st_i32(src, cpu_env, offs);
break;
default:
g_assert_not_reached();
}
}
static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr, static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
uint8_t es) uint8_t es)
@ -1304,3 +1350,22 @@ static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), &g[es]); get_field(s->fields, v3), &g[es]);
return DISAS_NEXT; return DISAS_NEXT;
} }
static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o)
{
TCGv_i32 tmp = tcg_temp_new_i32();
TCGv_i32 sum = tcg_temp_new_i32();
int i;
read_vec_element_i32(sum, get_field(s->fields, v3), 1, ES_32);
for (i = 0; i < 4; i++) {
read_vec_element_i32(tmp, get_field(s->fields, v2), i, ES_32);
tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp);
}
zero_vec(get_field(s->fields, v1));
write_vec_element_i32(sum, get_field(s->fields, v1), 1, ES_32);
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(sum);
return DISAS_NEXT;
}