qemu-sparc queue
-----BEGIN PGP SIGNATURE----- iQFSBAABCgA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAmR9xHseHG1hcmsuY2F2 ZS1heWxhbmRAaWxhbmRlLmNvLnVrAAoJEFvCxW+uDzIfFsgH/0lV2y9CphGdWwtV S/00CRhp5n0kv3P2m4yDvXBhBgMa8zS6m/ZHhcfuU5xOxkJAnPudvXiZucHP4TSy 6KFBgVi2+xBW1YJf2UEHlBG2cDnVDHtYQze6Ak3S+W5sVeZZU8n1k8k8kRwpuNDS io23oKXzzKMYErlwy12bEHEF7vpfcG9HktjpJxUtppkNDuPTysyKSA6BavEm3mJC MlIypbxqxgBvu2SJETeP/m1yLQOaswViCNkqNqUH+MgEc1ubtSCXEuXTfSHIsxLR 224kRPFciY1sm3NvG9yz75UYSq1JUvUC5mNIIqwjb4MZJ+YHqFb3S/6ilCYChQ8V IBPyvH0= =pxbI -----END PGP SIGNATURE----- Merge tag 'qemu-sparc-20230605' of https://github.com/mcayland/qemu into staging qemu-sparc queue # -----BEGIN PGP SIGNATURE----- # # iQFSBAABCgA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAmR9xHseHG1hcmsuY2F2 # ZS1heWxhbmRAaWxhbmRlLmNvLnVrAAoJEFvCxW+uDzIfFsgH/0lV2y9CphGdWwtV # S/00CRhp5n0kv3P2m4yDvXBhBgMa8zS6m/ZHhcfuU5xOxkJAnPudvXiZucHP4TSy # 6KFBgVi2+xBW1YJf2UEHlBG2cDnVDHtYQze6Ak3S+W5sVeZZU8n1k8k8kRwpuNDS # io23oKXzzKMYErlwy12bEHEF7vpfcG9HktjpJxUtppkNDuPTysyKSA6BavEm3mJC # MlIypbxqxgBvu2SJETeP/m1yLQOaswViCNkqNqUH+MgEc1ubtSCXEuXTfSHIsxLR # 224kRPFciY1sm3NvG9yz75UYSq1JUvUC5mNIIqwjb4MZJ+YHqFb3S/6ilCYChQ8V # IBPyvH0= # =pxbI # -----END PGP SIGNATURE----- # gpg: Signature made Mon 05 Jun 2023 04:18:19 AM PDT # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * tag 'qemu-sparc-20230605' of https://github.com/mcayland/qemu: hw/isa/i82378: Remove unused "io" attribute hw/arm/omap: Remove unused omap_uart_attach() hw/timer/i8254_common: Share "iobase" property via base class Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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commit
afa351fe36
@ -175,12 +175,3 @@ struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
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return s;
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}
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void omap_uart_attach(struct omap_uart_s *s, Chardev *chr)
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{
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/* TODO: Should reuse or destroy current s->serial */
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s->serial = serial_mm_init(get_system_memory(), s->base, 2, s->irq,
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omap_clk_getrate(s->fclk) / 16,
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chr ?: qemu_chr_new("null", "null", NULL),
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DEVICE_NATIVE_ENDIAN);
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}
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@ -301,7 +301,6 @@ static void kvm_pit_realizefn(DeviceState *dev, Error **errp)
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}
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static Property kvm_pit_properties[] = {
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DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1),
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DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", KVMPITState,
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lost_tick_policy, LOST_TICK_POLICY_DELAY),
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DEFINE_PROP_END_OF_LIST(),
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@ -34,7 +34,6 @@ struct I82378State {
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qemu_irq cpu_intr;
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qemu_irq *isa_irqs_in;
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MemoryRegion io;
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};
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static const VMStateDescription vmstate_i82378 = {
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@ -350,11 +350,6 @@ static void pit_realizefn(DeviceState *dev, Error **errp)
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pc->parent_realize(dev, errp);
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}
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static Property pit_properties[] = {
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DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pit_class_initfn(ObjectClass *klass, void *data)
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{
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PITClass *pc = PIT_CLASS(klass);
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@ -366,7 +361,6 @@ static void pit_class_initfn(ObjectClass *klass, void *data)
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k->get_channel_info = pit_get_channel_info_common;
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k->post_load = pit_post_load;
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dc->reset = pit_reset;
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device_class_set_props(dc, pit_properties);
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}
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static const TypeInfo pit_info = {
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@ -240,6 +240,11 @@ static const VMStateDescription vmstate_pit_common = {
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}
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};
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static Property pit_common_properties[] = {
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DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pit_common_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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@ -252,6 +257,7 @@ static void pit_common_class_init(ObjectClass *klass, void *data)
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* done by board code.
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*/
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dc->user_creatable = false;
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device_class_set_props(dc, pit_common_properties);
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}
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static const TypeInfo pit_common_type = {
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@ -724,7 +724,6 @@ struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
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qemu_irq txdma, qemu_irq rxdma,
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const char *label, Chardev *chr);
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void omap_uart_reset(struct omap_uart_s *s);
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void omap_uart_attach(struct omap_uart_s *s, Chardev *chr);
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struct omap_mpuio_s;
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qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
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