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aspeed/smc: Add support for address lane disablement

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The controller can be configured to disable or enable address and data
byte lanes when issuing commands. This is useful in read command mode
to send SPI NOR commands that don't have an address space, such as
RDID. It's a good way to have a unified read operation for registers
and flash contents accesses.

A new SPI driver proposed by Aspeed makes use of this feature. Add
support for address lanes to start with. We will do the same for the
data lanes if they are controlled one day.

Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20201120161547.740806-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Cédric Le Goater 2020-12-10 12:11:03 +01:00
parent e01b4d5b6e
commit af453a5ef5
1 changed files with 18 additions and 7 deletions
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25
hw/ssi/aspeed_smc.c
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@ -71,6 +71,16 @@
#define INTR_CTRL_CMD_ABORT_EN (1 << 2) #define INTR_CTRL_CMD_ABORT_EN (1 << 2)
#define INTR_CTRL_WRITE_PROTECT_EN (1 << 1) #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1)
/* Command Control Register */
#define R_CE_CMD_CTRL (0x0C / 4)
#define CTRL_ADDR_BYTE0_DISABLE_SHIFT 4
#define CTRL_DATA_BYTE0_DISABLE_SHIFT 0
#define aspeed_smc_addr_byte_enabled(s, i) \
(!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i)))))
#define aspeed_smc_data_byte_enabled(s, i) \
(!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i)))))
/* CEx Control Register */ /* CEx Control Register */
#define R_CTRL0 (0x10 / 4) #define R_CTRL0 (0x10 / 4)
#define CTRL_IO_QPI (1 << 31) #define CTRL_IO_QPI (1 << 31)
@ -702,19 +712,17 @@ static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)
{ {
const AspeedSMCState *s = fl->controller; const AspeedSMCState *s = fl->controller;
uint8_t cmd = aspeed_smc_flash_cmd(fl); uint8_t cmd = aspeed_smc_flash_cmd(fl);
int i; int i = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
/* Flash access can not exceed CS segment */ /* Flash access can not exceed CS segment */
addr = aspeed_smc_check_segment_addr(fl, addr); addr = aspeed_smc_check_segment_addr(fl, addr);
ssi_transfer(s->spi, cmd); ssi_transfer(s->spi, cmd);
while (i--) {
if (aspeed_smc_flash_is_4byte(fl)) { if (aspeed_smc_addr_byte_enabled(s, i)) {
ssi_transfer(s->spi, (addr >> 24) & 0xff); ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff);
}
} }
ssi_transfer(s->spi, (addr >> 16) & 0xff);
ssi_transfer(s->spi, (addr >> 8) & 0xff);
ssi_transfer(s->spi, (addr & 0xff));
/* /*
* Use fake transfers to model dummy bytes. The value should * Use fake transfers to model dummy bytes. The value should
@ -988,6 +996,7 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
(addr >= s->r_timings && (addr >= s->r_timings &&
addr < s->r_timings + s->ctrl->nregs_timings) || addr < s->r_timings + s->ctrl->nregs_timings) ||
addr == s->r_ce_ctrl || addr == s->r_ce_ctrl ||
addr == R_CE_CMD_CTRL ||
addr == R_INTR_CTRL || addr == R_INTR_CTRL ||
addr == R_DUMMY_DATA || addr == R_DUMMY_DATA ||
(s->ctrl->has_dma && addr == R_DMA_CTRL) || (s->ctrl->has_dma && addr == R_DMA_CTRL) ||
@ -1276,6 +1285,8 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
if (value != s->regs[R_SEG_ADDR0 + cs]) { if (value != s->regs[R_SEG_ADDR0 + cs]) {
aspeed_smc_flash_set_segment(s, cs, value); aspeed_smc_flash_set_segment(s, cs, value);
} }
} else if (addr == R_CE_CMD_CTRL) {
s->regs[addr] = value & 0xff;
} else if (addr == R_DUMMY_DATA) { } else if (addr == R_DUMMY_DATA) {
s->regs[addr] = value & 0xff; s->regs[addr] = value & 0xff;
} else if (addr == R_INTR_CTRL) { } else if (addr == R_INTR_CTRL) {