acpi/gpex: Exclude pxb's resources from PCI0
Exclude the resources of extra root bridges from PCI0's _CRS. Otherwise, the resource windows would overlap in guest, and the IO resource window would fail to be registered. Acked-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Jiahui Cen <cenjiahui@huawei.com> Message-Id: <20210114100643.10617-6-cenjiahui@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -146,6 +146,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
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Aml *method, *crs, *dev, *rbuf;
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Aml *method, *crs, *dev, *rbuf;
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PCIBus *bus = cfg->bus;
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PCIBus *bus = cfg->bus;
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CrsRangeSet crs_range_set;
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CrsRangeSet crs_range_set;
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CrsRangeEntry *entry;
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int i;
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/* start to construct the tables for pxb */
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/* start to construct the tables for pxb */
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crs_range_set_init(&crs_range_set);
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crs_range_set_init(&crs_range_set);
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@ -193,7 +195,6 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
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aml_append(scope, dev);
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aml_append(scope, dev);
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}
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}
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}
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}
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crs_range_set_free(&crs_range_set);
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/* tables for the main */
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/* tables for the main */
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dev = aml_device("%s", "PCI0");
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dev = aml_device("%s", "PCI0");
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@ -211,36 +212,55 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
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aml_append(method, aml_return(aml_int(cfg->ecam.base)));
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aml_append(method, aml_return(aml_int(cfg->ecam.base)));
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aml_append(dev, method);
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aml_append(dev, method);
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/*
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* At this point crs_range_set has all the ranges used by pci
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* busses *other* than PCI0. These ranges will be excluded from
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* the PCI0._CRS.
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*/
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rbuf = aml_resource_template();
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rbuf = aml_resource_template();
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aml_append(rbuf,
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aml_append(rbuf,
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aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
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0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
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nr_pcie_buses));
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nr_pcie_buses));
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if (cfg->mmio32.size) {
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if (cfg->mmio32.size) {
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aml_append(rbuf,
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crs_replace_with_free_ranges(crs_range_set.mem_ranges,
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aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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cfg->mmio32.base,
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AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
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cfg->mmio32.base + cfg->mmio32.size - 1);
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cfg->mmio32.base,
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for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
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cfg->mmio32.base + cfg->mmio32.size - 1,
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entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
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0x0000,
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aml_append(rbuf,
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cfg->mmio32.size));
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aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
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entry->base, entry->limit,
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0x0000, entry->limit - entry->base + 1));
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}
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}
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}
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if (cfg->pio.size) {
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if (cfg->pio.size) {
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aml_append(rbuf,
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crs_replace_with_free_ranges(crs_range_set.io_ranges,
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aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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0x0000,
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AML_ENTIRE_RANGE, 0x0000, 0x0000,
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cfg->pio.size - 1);
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cfg->pio.size - 1,
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for (i = 0; i < crs_range_set.io_ranges->len; i++) {
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cfg->pio.base,
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entry = g_ptr_array_index(crs_range_set.io_ranges, i);
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cfg->pio.size));
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aml_append(rbuf,
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aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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AML_ENTIRE_RANGE, 0x0000, entry->base,
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entry->limit, cfg->pio.base,
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entry->limit - entry->base + 1));
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}
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}
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}
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if (cfg->mmio64.size) {
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if (cfg->mmio64.size) {
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aml_append(rbuf,
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crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
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aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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cfg->mmio64.base,
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AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
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cfg->mmio64.base + cfg->mmio64.size - 1);
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cfg->mmio64.base,
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for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
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cfg->mmio64.base + cfg->mmio64.size - 1,
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entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
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0x0000,
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aml_append(rbuf,
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cfg->mmio64.size));
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aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
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entry->base,
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entry->limit, 0x0000,
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entry->limit - entry->base + 1));
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}
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}
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}
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aml_append(dev, aml_name_decl("_CRS", rbuf));
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aml_append(dev, aml_name_decl("_CRS", rbuf));
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@ -259,4 +279,6 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
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aml_append(dev_res0, aml_name_decl("_CRS", crs));
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aml_append(dev_res0, aml_name_decl("_CRS", crs));
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aml_append(dev, dev_res0);
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aml_append(dev, dev_res0);
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aml_append(scope, dev);
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aml_append(scope, dev);
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crs_range_set_free(&crs_range_set);
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}
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}
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