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target-openrisc: Correct wrong epcr register in interrupt handler

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This patch corrects several misbehaviors during an interrupt process.
Most of the time the pc is already correct and therefore no special treatment
of the exceptions is necessary.

Tested by checking crashing programs which otherwise work in or1ksim.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
Reviewed-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Jia Liu <proljc@gmail.com>
This commit is contained in:
Sebastian Macke 2013-10-22 02:12:40 +02:00 committed by Jia Liu
parent 04359e6bb7
commit ae52bd96ce
1 changed files with 7 additions and 18 deletions
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25
target-openrisc/interrupt.c
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@ -30,26 +30,15 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUOpenRISCState *env = &cpu->env;
#ifndef CONFIG_USER_ONLY
if (env->flags & D_FLAG) { /* Delay Slot insn */
env->epcr = env->pc;
if (env->flags & D_FLAG) {
env->flags &= ~D_FLAG;
env->sr |= SR_DSX;
if (env->exception_index == EXCP_TICK ||
env->exception_index == EXCP_INT ||
env->exception_index == EXCP_SYSCALL ||
env->exception_index == EXCP_FPE) {
env->epcr = env->jmp_pc;
} else {
env->epcr = env->pc - 4;
}
} else {
if (env->exception_index == EXCP_TICK ||
env->exception_index == EXCP_INT ||
env->exception_index == EXCP_SYSCALL ||
env->exception_index == EXCP_FPE) {
env->epcr = env->npc;
} else {
env->epcr = env->pc;
}
env->epcr -= 4;
}
if (env->exception_index == EXCP_SYSCALL) {
env->epcr += 4;
}
/* For machine-state changed between user-mode and supervisor mode,