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target/arm: Convert T16, Reverse bytes

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-59-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-09-04 12:30:48 -07:00 committed by Peter Maydell
parent 20556e7bd6
commit ae3002b021
2 changed files with 12 additions and 15 deletions
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9
target/arm/t16.decode
View File

@ -24,6 +24,7 @@
&s_rri_rot !extern s rn rd imm rot
&s_rrrr !extern s rd rn rm ra
&rrr_rot !extern rd rn rm rot
&rr !extern rd rm
&ri !extern rd imm
&r !extern rm
&ldst_rr !extern p w u rn rt rm shimm shtype
@ -195,3 +196,11 @@ SETEND 1011 0110 010 1 E:1 000 &setend
CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod
CPS_v7m 1011 0110 011 im:1 00 I:1 F:1
}
# Reverse bytes
@rdm .... .... .. rm:3 rd:3 &rr
REV 1011 1010 00 ... ... @rdm
REV16 1011 1010 01 ... ... @rdm
REVSH 1011 1010 11 ... ... @rdm

18
target/arm/translate.c
View File

@ -10730,7 +10730,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
uint32_t val, op, rm, rn, rd, shift, cond;
uint32_t val, op, rm, rd, shift, cond;
int32_t offset;
int i;
TCGv_i32 tmp;
@ -10927,20 +10927,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
break;
}
/* Otherwise this is rev */
ARCH(6);
rn = (insn >> 3) & 0x7;
rd = insn & 0x7;
tmp = load_reg(s, rn);
switch (op1) {
case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
case 1: gen_rev16(tmp, tmp); break;
case 3: gen_revsh(tmp, tmp); break;
default:
g_assert_not_reached();
}
store_reg(s, rd, tmp);
break;
/* Otherwise this is rev, in decodetree */
goto illegal_op;
}
case 6: /* setend, cps; in decodetree */