From ae1c1a3d68c75ebc5487f123c73dcfff5844b02a Mon Sep 17 00:00:00 2001
From: aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Mon, 12 Jan 2009 21:33:02 +0000
Subject: [PATCH] target-ppc: add altivec cache instructions

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6275 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-ppc/translate.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6bb81d2ad6..0cfcc0872d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -4152,6 +4152,33 @@ GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
     tcg_temp_free(t0);
 }
 
+/* dst / dstt */
+GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
+{
+    if (rA(ctx->opcode) == 0) {
+        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
+    } else {
+        /* interpreted as no-op */
+    }
+}
+
+/* dstst /dststt */
+GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
+{
+    if (rA(ctx->opcode) == 0) {
+        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
+    } else {
+        /* interpreted as no-op */
+    }
+
+}
+
+/* dss / dssall */
+GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
+{
+    /* interpreted as no-op */
+}
+
 /* icbi */
 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
 {