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target/riscv: Promote svade to a normal extension

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Named features are extensions which don't make sense for users to
control and are therefore not exposed on the command line. However,
svade is an extension which makes sense for users to control, so treat
it like a "normal" extension. The default is false, even for the max
cpu type, since QEMU has always implemented hardware A/D PTE bit
updating, so users must opt into svade (or get it from a CPU type
which enables it by default).

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240215223955.969568-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Andrew Jones 2024-02-15 19:39:55 -03:00 committed by Alistair Francis
parent 70d22fd92c
commit adb49752dd
2 changed files with 8 additions and 7 deletions
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9
target/riscv/cpu.c
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@ -1474,6 +1474,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true), MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
@ -1589,7 +1590,6 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
* and priv_ver like regular extensions. * and priv_ver like regular extensions.
*/ */
const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = { const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
MULTI_EXT_CFG_BOOL("svade", ext_svade, true),
MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
/* /*
@ -2237,8 +2237,6 @@ static RISCVCPUProfile RVA22U64 = {
* Other named features that we already implement: Sstvecd, Sstvala, * Other named features that we already implement: Sstvecd, Sstvala,
* Sscounterenw * Sscounterenw
* *
* Named features that we need to enable: svade
*
* The remaining features/extensions comes from RVA22U64. * The remaining features/extensions comes from RVA22U64.
*/ */
static RISCVCPUProfile RVA22S64 = { static RISCVCPUProfile RVA22S64 = {
@ -2250,10 +2248,7 @@ static RISCVCPUProfile RVA22S64 = {
.ext_offsets = { .ext_offsets = {
/* rva22s64 exts */ /* rva22s64 exts */
CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt), CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt),
CPU_CFG_OFFSET(ext_svinval), CPU_CFG_OFFSET(ext_svinval), CPU_CFG_OFFSET(ext_svade),
/* rva22s64 named features */
CPU_CFG_OFFSET(ext_svade),
RISCV_PROFILE_EXT_LIST_END RISCV_PROFILE_EXT_LIST_END
} }

6
target/riscv/tcg/tcg-cpu.c
View File

@ -1282,6 +1282,12 @@ static void riscv_init_max_cpu_extensions(Object *obj)
isa_ext_update_enabled(cpu, prop->offset, true); isa_ext_update_enabled(cpu, prop->offset, true);
} }
/*
* Some extensions can't be added without backward compatibilty concerns.
* Disable those, the user can still opt in to them on the command line.
*/
cpu->cfg.ext_svade = false;
/* set vector version */ /* set vector version */
env->vext_ver = VEXT_VERSION_1_00_0; env->vext_ver = VEXT_VERSION_1_00_0;