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linux-user: Implement CPU-specific signal handler for loongarch64 hosts

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Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-30-git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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WANG Xuerui 2021-12-21 13:41:03 +08:00 committed by Richard Henderson
parent 6016b7b46e
commit ad812c3bd6
1 changed files with 87 additions and 0 deletions
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87
linux-user/host/loongarch64/host-signal.h Normal file
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/*
* host-signal.h: signal info dependent on the host architecture
*
* Copyright (c) 2003-2005 Fabrice Bellard
* Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
*
* This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef LOONGARCH64_HOST_SIGNAL_H
#define LOONGARCH64_HOST_SIGNAL_H
static inline uintptr_t host_signal_pc(ucontext_t *uc)
{
return uc->uc_mcontext.__pc;
}
static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc)
{
uc->uc_mcontext.__pc = pc;
}
static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
{
const uint32_t *pinsn = (const uint32_t *)host_signal_pc(uc);
uint32_t insn = pinsn[0];
/* Detect store by reading the instruction at the program counter. */
switch ((insn >> 26) & 0b111111) {
case 0b001000: /* {ll,sc}.[wd] */
switch ((insn >> 24) & 0b11) {
case 0b01: /* sc.w */
case 0b11: /* sc.d */
return true;
}
break;
case 0b001001: /* {ld,st}ox4.[wd] ({ld,st}ptr.[wd]) */
switch ((insn >> 24) & 0b11) {
case 0b01: /* stox4.w (stptr.w) */
case 0b11: /* stox4.d (stptr.d) */
return true;
}
break;
case 0b001010: /* {ld,st}.* family */
switch ((insn >> 22) & 0b1111) {
case 0b0100: /* st.b */
case 0b0101: /* st.h */
case 0b0110: /* st.w */
case 0b0111: /* st.d */
case 0b1101: /* fst.s */
case 0b1111: /* fst.d */
return true;
}
break;
case 0b001110: /* indexed, atomic, bounds-checking memory operations */
uint32_t sel = (insn >> 15) & 0b11111111111;
switch (sel) {
case 0b00000100000: /* stx.b */
case 0b00000101000: /* stx.h */
case 0b00000110000: /* stx.w */
case 0b00000111000: /* stx.d */
case 0b00001110000: /* fstx.s */
case 0b00001111000: /* fstx.d */
case 0b00011101100: /* fstgt.s */
case 0b00011101101: /* fstgt.d */
case 0b00011101110: /* fstle.s */
case 0b00011101111: /* fstle.d */
case 0b00011111000: /* stgt.b */
case 0b00011111001: /* stgt.h */
case 0b00011111010: /* stgt.w */
case 0b00011111011: /* stgt.d */
case 0b00011111100: /* stle.b */
case 0b00011111101: /* stle.h */
case 0b00011111110: /* stle.w */
case 0b00011111111: /* stle.d */
case 0b00011000000 ... 0b00011100011: /* am* insns */
return true;
}
break;
}
return false;
}
#endif