target/ppc/cpu.h: Clean up comments in the struct CPUPPCState definition
The cpu env struct is quite complex but comments supposed to explain it in its definition just make it harder to read. Reformat and reword some comments to make it clearer and more readable. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <8707144ab1ccf9c5c89a39c2d7a0b02307ca25d4.1581888834.git.balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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BALATON Zoltan
David Gibson
parent
b561615db2
commit
ad5db2e732
127
target/ppc/cpu.h
127
target/ppc/cpu.h
@ -960,63 +960,44 @@ struct ppc_radix_page_info {
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#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
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struct CPUPPCState {
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/*
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* First are the most commonly used resources during translated
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* code execution
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*/
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/* general purpose registers */
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target_ulong gpr[32];
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/* Storage for GPR MSB, used by the SPE extension */
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target_ulong gprh[32];
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/* LR */
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/* Most commonly used resources during translated code execution first */
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target_ulong gpr[32]; /* general purpose registers */
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target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
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target_ulong lr;
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/* CTR */
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target_ulong ctr;
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/* condition register */
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uint32_t crf[8];
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uint32_t crf[8]; /* condition register */
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#if defined(TARGET_PPC64)
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/* CFAR */
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target_ulong cfar;
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#endif
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/* XER (with SO, OV, CA split out) */
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target_ulong xer;
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target_ulong xer; /* XER (with SO, OV, CA split out) */
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target_ulong so;
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target_ulong ov;
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target_ulong ca;
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target_ulong ov32;
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target_ulong ca32;
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/* Reservation address */
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target_ulong reserve_addr;
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/* Reservation value */
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target_ulong reserve_val;
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target_ulong reserve_addr; /* Reservation address */
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target_ulong reserve_val; /* Reservation value */
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target_ulong reserve_val2;
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/* Those ones are used in supervisor mode only */
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/* machine state register */
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target_ulong msr;
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/* temporary general purpose registers */
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target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
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/* These are used in supervisor mode only */
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target_ulong msr; /* machine state register */
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target_ulong tgpr[4]; /* temporary general purpose registers, */
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/* used to speed-up TLB assist handlers */
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/* Next instruction pointer */
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target_ulong nip;
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/* High part of 128-bit helper return. */
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uint64_t retxh;
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target_ulong nip; /* next instruction pointer */
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uint64_t retxh; /* high part of 128-bit helper return */
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/* when a memory exception occurs, the access type is stored here */
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int access_type;
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/* MMU context - only relevant for full system emulation */
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#if !defined(CONFIG_USER_ONLY)
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/* MMU context, only relevant for full system emulation */
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#if defined(TARGET_PPC64)
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/* PowerPC 64 SLB area */
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ppc_slb_t slb[MAX_SLB_ENTRIES];
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/* tcg TLB needs flush (deferred slb inval instruction typically) */
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ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
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#endif
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/* segment registers */
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target_ulong sr[32];
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/* BATs */
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uint32_t nb_BATs;
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target_ulong sr[32]; /* segment registers */
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uint32_t nb_BATs; /* number of BATs */
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target_ulong DBAT[2][8];
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target_ulong IBAT[2][8];
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/* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
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@ -1028,8 +1009,7 @@ struct CPUPPCState {
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int nb_pids; /* Number of available PID registers */
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int tlb_type; /* Type of TLB we're dealing with */
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ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
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/* 403 dedicated access protection registers */
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target_ulong pb[4];
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target_ulong pb[4]; /* 403 dedicated access protection registers */
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bool tlb_dirty; /* Set to non-zero when modifying TLB */
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bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
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uint32_t tlb_need_flush; /* Delayed flush needed */
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@ -1038,38 +1018,30 @@ struct CPUPPCState {
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#endif
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/* Other registers */
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/* Special purpose registers */
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target_ulong spr[1024];
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target_ulong spr[1024]; /* special purpose registers */
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ppc_spr_t spr_cb[1024];
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/* Vector status and control register, minus VSCR_SAT. */
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/* Vector status and control register, minus VSCR_SAT */
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uint32_t vscr;
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/* VSX registers (including FP and AVR) */
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ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
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/* Non-zero if and only if VSCR_SAT should be set. */
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/* Non-zero if and only if VSCR_SAT should be set */
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ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
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/* SPE registers */
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uint64_t spe_acc;
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uint32_t spe_fscr;
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/*
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* SPE and Altivec can share a status since they will never be
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* used simultaneously
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*/
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/* SPE and Altivec share status as they'll never be used simultaneously */
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float_status vec_status;
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/* Floating point execution context */
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float_status fp_status;
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/* floating point status and control register */
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target_ulong fpscr;
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float_status fp_status; /* Floating point execution context */
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target_ulong fpscr; /* Floating point status and control register */
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/* Internal devices resources */
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/* Time base and decrementer */
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ppc_tb_t *tb_env;
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/* Device control registers */
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ppc_dcr_t *dcr_env;
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ppc_tb_t *tb_env; /* Time base and decrementer */
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ppc_dcr_t *dcr_env; /* Device control registers */
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int dcache_line_size;
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int icache_line_size;
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/* Those resources are used during exception processing */
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/* These resources are used during exception processing */
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/* CPU model definition */
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target_ulong msr_mask;
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powerpc_mmu_t mmu_model;
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@ -1088,58 +1060,49 @@ struct CPUPPCState {
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uint32_t pending_interrupts;
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#if !defined(CONFIG_USER_ONLY)
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/*
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* This is the IRQ controller, which is implementation dependent
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* and only relevant when emulating a complete machine. Note that
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* this isn't used by recent Book3s compatible CPUs (POWER7 and
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* newer).
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* This is the IRQ controller, which is implementation dependent and only
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* relevant when emulating a complete machine. Note that this isn't used
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* by recent Book3s compatible CPUs (POWER7 and newer).
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*/
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uint32_t irq_input_state;
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void **irq_inputs;
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/* Exception vectors */
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target_ulong excp_vectors[POWERPC_EXCP_NB];
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target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
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target_ulong excp_prefix;
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target_ulong ivor_mask;
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target_ulong ivpr_mask;
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target_ulong hreset_vector;
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hwaddr mpic_iack;
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/* true when the external proxy facility mode is enabled */
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bool mpic_proxy;
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bool mpic_proxy; /* true if the external proxy facility mode is enabled */
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bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
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/* instructions and SPRs are diallowed if MSR:HV is 0 */
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/*
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* set when the processor has an HV mode, thus HV priv
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* instructions and SPRs are diallowed if MSR:HV is 0
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*/
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bool has_hv_mode;
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/*
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* On P7/P8/P9, set when in PM state, we need to handle resume in
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* a special way (such as routing some resume causes to 0x100, ie,
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* sreset), so flag this here.
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* On P7/P8/P9, set when in PM state so we need to handle resume in a
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* special way (such as routing some resume causes to 0x100, i.e. sreset).
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*/
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bool resume_as_sreset;
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#endif
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/* Those resources are used only in QEMU core */
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target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
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/* These resources are used only in QEMU core */
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target_ulong hflags; /* hflags is MSR & HFLAGS_MASK */
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target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
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int immu_idx; /* precomputed MMU index to speed up insn access */
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int immu_idx; /* precomputed MMU index to speed up insn accesses */
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int dmmu_idx; /* precomputed MMU index to speed up data accesses */
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/* Power management */
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int (*check_pow)(CPUPPCState *env);
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#if !defined(CONFIG_USER_ONLY)
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void *load_info; /* Holds boot loading state. */
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void *load_info; /* holds boot loading state */
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#endif
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/* booke timers */
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/*
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* Specifies bit locations of the Time Base used to signal a fixed
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* timer exception on a transition from 0 to 1. (watchdog or
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* fixed-interval timer)
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* Specifies bit locations of the Time Base used to signal a fixed timer
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* exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
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*
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* 0 selects the least significant bit.
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* 63 selects the most significant bit.
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* 0 selects the least significant bit, 63 selects the most significant bit
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*/
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uint8_t fit_period[4];
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uint8_t wdt_period[4];
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