e1000e: Notify only new interrupts
In MSI-X mode, if there are interrupts already notified but not cleared and a new interrupt arrives, e1000e incorrectly notifies the notified ones again along with the new one. To fix this issue, replace e1000e_update_interrupt_state() with two new functions: e1000e_raise_interrupts() and e1000e_lower_interrupts(). These functions don't only raise or lower interrupts, but it also performs register writes which updates the interrupt state. Before it performs a register write, these function determines the interrupts already raised, and compares with the interrupts raised after the register write to determine the interrupts to notify. The introduction of these functions made tracepoints which assumes that the caller of e1000e_update_interrupt_state() performs register writes obsolete. These tracepoints are now removed, and alternative ones are added to the new functions. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
This commit is contained in:
Akihiko Odaki
Jason Wang
parent
3dfc616eab
commit
ad431f0f82
@ -165,14 +165,14 @@ e1000e_intrmgr_on_throttling_timer(void *opaque)
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timer->running = false;
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if (msi_enabled(timer->core->owner)) {
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trace_e1000e_irq_msi_notify_postponed();
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/* Clear msi_causes_pending to fire MSI eventually */
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timer->core->msi_causes_pending = 0;
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e1000e_set_interrupt_cause(timer->core, 0);
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} else {
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trace_e1000e_irq_legacy_notify_postponed();
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e1000e_set_interrupt_cause(timer->core, 0);
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if (timer->core->mac[IMS] & timer->core->mac[ICR]) {
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if (msi_enabled(timer->core->owner)) {
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trace_e1000e_irq_msi_notify_postponed();
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msi_notify(timer->core->owner, 0);
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} else {
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trace_e1000e_irq_legacy_notify_postponed();
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e1000e_raise_legacy_irq(timer->core);
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}
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}
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}
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@ -366,10 +366,6 @@ static void
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e1000e_intrmgr_fire_all_timers(E1000ECore *core)
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{
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int i;
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uint32_t val = e1000e_intmgr_collect_delayed_causes(core);
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trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]);
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core->mac[ICR] |= val;
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if (core->itr.running) {
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timer_del(core->itr.timer);
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@ -1974,13 +1970,6 @@ void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE])
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}
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};
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static inline void
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e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits)
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{
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trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits);
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core->mac[IMS] &= ~bits;
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}
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static inline bool
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e1000e_postpone_interrupt(E1000IntrDelayTimer *timer)
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{
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@ -2038,7 +2027,6 @@ e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
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effective_eiac = core->mac[EIAC] & cause;
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core->mac[ICR] &= ~effective_eiac;
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core->msi_causes_pending &= ~effective_eiac;
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if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
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core->mac[IMS] &= ~effective_eiac;
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@ -2130,33 +2118,17 @@ e1000e_fix_icr_asserted(E1000ECore *core)
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trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]);
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}
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static void
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e1000e_send_msi(E1000ECore *core, bool msix)
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static void e1000e_raise_interrupts(E1000ECore *core,
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size_t index, uint32_t causes)
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{
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uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED;
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core->msi_causes_pending &= causes;
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causes ^= core->msi_causes_pending;
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if (causes == 0) {
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return;
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}
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core->msi_causes_pending |= causes;
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if (msix) {
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e1000e_msix_notify(core, causes);
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} else {
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if (!e1000e_itr_should_postpone(core)) {
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trace_e1000e_irq_msi_notify(causes);
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msi_notify(core->owner, 0);
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}
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}
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}
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static void
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e1000e_update_interrupt_state(E1000ECore *core)
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{
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bool interrupts_pending;
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bool is_msix = msix_enabled(core->owner);
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uint32_t old_causes = core->mac[IMS] & core->mac[ICR];
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uint32_t raised_causes;
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trace_e1000e_irq_set(index << 2,
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core->mac[index], core->mac[index] | causes);
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core->mac[index] |= causes;
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/* Set ICR[OTHER] for MSI-X */
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if (is_msix) {
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@ -2178,40 +2150,58 @@ e1000e_update_interrupt_state(E1000ECore *core)
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*/
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core->mac[ICS] = core->mac[ICR];
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interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false;
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if (!interrupts_pending) {
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core->msi_causes_pending = 0;
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trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
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core->mac[ICR], core->mac[IMS]);
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raised_causes = core->mac[IMS] & core->mac[ICR] & ~old_causes;
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if (!raised_causes) {
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return;
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}
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if (is_msix) {
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e1000e_msix_notify(core, raised_causes & ~E1000_ICR_ASSERTED);
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} else if (!e1000e_itr_should_postpone(core)) {
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if (msi_enabled(core->owner)) {
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trace_e1000e_irq_msi_notify(raised_causes);
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msi_notify(core->owner, 0);
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} else {
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e1000e_raise_legacy_irq(core);
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}
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}
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}
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static void e1000e_lower_interrupts(E1000ECore *core,
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size_t index, uint32_t causes)
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{
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trace_e1000e_irq_clear(index << 2,
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core->mac[index], core->mac[index] & ~causes);
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core->mac[index] &= ~causes;
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/*
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* Make sure ICR and ICS registers have the same value.
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* The spec says that the ICS register is write-only. However in practice,
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* on real hardware ICS is readable, and for reads it has the same value as
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* ICR (except that ICS does not have the clear on read behaviour of ICR).
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*
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* The VxWorks PRO/1000 driver uses this behaviour.
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*/
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core->mac[ICS] = core->mac[ICR];
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trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
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core->mac[ICR], core->mac[IMS]);
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if (is_msix || msi_enabled(core->owner)) {
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if (interrupts_pending) {
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e1000e_send_msi(core, is_msix);
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}
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} else {
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if (interrupts_pending) {
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if (!e1000e_itr_should_postpone(core)) {
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e1000e_raise_legacy_irq(core);
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}
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} else {
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e1000e_lower_legacy_irq(core);
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}
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if (!(core->mac[IMS] & core->mac[ICR]) &&
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!msix_enabled(core->owner) && !msi_enabled(core->owner)) {
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e1000e_lower_legacy_irq(core);
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}
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}
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static void
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e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val)
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{
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trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]);
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val |= e1000e_intmgr_collect_delayed_causes(core);
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core->mac[ICR] |= val;
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trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]);
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e1000e_update_interrupt_state(core);
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e1000e_raise_interrupts(core, ICR, val);
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}
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static inline void
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@ -2477,30 +2467,27 @@ e1000e_set_ics(E1000ECore *core, int index, uint32_t val)
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static void
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e1000e_set_icr(E1000ECore *core, int index, uint32_t val)
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{
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uint32_t icr = 0;
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if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
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(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
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trace_e1000e_irq_icr_process_iame();
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e1000e_clear_ims_bits(core, core->mac[IAM]);
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e1000e_lower_interrupts(core, IMS, core->mac[IAM]);
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}
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icr = core->mac[ICR] & ~val;
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/*
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* Windows driver expects that the "receive overrun" bit and other
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* ones to be cleared when the "Other" bit (#24) is cleared.
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*/
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icr = (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : icr;
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trace_e1000e_irq_icr_write(val, core->mac[ICR], icr);
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core->mac[ICR] = icr;
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e1000e_update_interrupt_state(core);
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if (val & E1000_ICR_OTHER) {
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val |= E1000_ICR_OTHER_CAUSES;
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}
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e1000e_lower_interrupts(core, ICR, val);
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}
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static void
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e1000e_set_imc(E1000ECore *core, int index, uint32_t val)
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{
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trace_e1000e_irq_ims_clear_set_imc(val);
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e1000e_clear_ims_bits(core, val);
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e1000e_update_interrupt_state(core);
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e1000e_lower_interrupts(core, IMS, val);
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}
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static void
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@ -2521,9 +2508,6 @@ e1000e_set_ims(E1000ECore *core, int index, uint32_t val)
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uint32_t valid_val = val & ims_valid_mask;
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trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val);
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core->mac[IMS] |= valid_val;
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if ((valid_val & ims_ext_mask) &&
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(core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) &&
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msix_enabled(core->owner)) {
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@ -2536,7 +2520,7 @@ e1000e_set_ims(E1000ECore *core, int index, uint32_t val)
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e1000e_intrmgr_fire_all_timers(core);
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}
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e1000e_update_interrupt_state(core);
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e1000e_raise_interrupts(core, IMS, valid_val);
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}
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static void
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@ -2609,28 +2593,25 @@ static uint32_t
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e1000e_mac_icr_read(E1000ECore *core, int index)
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{
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uint32_t ret = core->mac[ICR];
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trace_e1000e_irq_icr_read_entry(ret);
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if (core->mac[IMS] == 0) {
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trace_e1000e_irq_icr_clear_zero_ims();
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core->mac[ICR] = 0;
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e1000e_lower_interrupts(core, ICR, 0xffffffff);
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}
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if (!msix_enabled(core->owner)) {
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trace_e1000e_irq_icr_clear_nonmsix_icr_read();
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core->mac[ICR] = 0;
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e1000e_lower_interrupts(core, ICR, 0xffffffff);
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}
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if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
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(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
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trace_e1000e_irq_icr_clear_iame();
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core->mac[ICR] = 0;
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e1000e_lower_interrupts(core, ICR, 0xffffffff);
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trace_e1000e_irq_icr_process_iame();
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e1000e_clear_ims_bits(core, core->mac[IAM]);
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e1000e_lower_interrupts(core, IMS, core->mac[IAM]);
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}
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trace_e1000e_irq_icr_read_exit(core->mac[ICR]);
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e1000e_update_interrupt_state(core);
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return ret;
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}
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@ -111,8 +111,6 @@ struct E1000Core {
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PCIDevice *owner;
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void (*owner_start_recv)(PCIDevice *d);
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uint32_t msi_causes_pending;
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int64_t timadj;
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};
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@ -205,6 +205,8 @@ e1000e_irq_msix_notify_postponed_vec(int idx) "Sending MSI-X postponed by EITR[%
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e1000e_irq_legacy_notify(bool level) "IRQ line state: %d"
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e1000e_irq_msix_notify_vec(uint32_t vector) "MSI-X notify vector 0x%x"
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e1000e_irq_postponed_by_xitr(uint32_t reg) "Interrupt postponed by [E]ITR register 0x%x"
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e1000e_irq_clear(uint32_t offset, uint32_t old, uint32_t new) "Clearing interrupt register 0x%x: 0x%x --> 0x%x"
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e1000e_irq_set(uint32_t offset, uint32_t old, uint32_t new) "Setting interrupt register 0x%x: 0x%x --> 0x%x"
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e1000e_irq_clear_ims(uint32_t bits, uint32_t old_ims, uint32_t new_ims) "Clearing IMS bits 0x%x: 0x%x --> 0x%x"
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e1000e_irq_set_ims(uint32_t bits, uint32_t old_ims, uint32_t new_ims) "Setting IMS bits 0x%x: 0x%x --> 0x%x"
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e1000e_irq_fix_icr_asserted(uint32_t new_val) "ICR_ASSERTED bit fixed: 0x%x"
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