mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target-mips: generate a reserved instruction exception on CPU without DSP

Browse Source 
On CPU without DSP ASE support, a reserved instruction exception (instead of
a DSP ASE sate disabled) should be generated.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2013-01-01 18:02:23 +01:00
parent d75c135e6b
commit ad153f153d
1 changed files with 10 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
target-mips/translate.c
View File

@ -1394,14 +1394,22 @@ static inline void check_cp1_registers(DisasContext *ctx, int regs)
static inline void check_dsp(DisasContext *ctx) static inline void check_dsp(DisasContext *ctx)
{ {
if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) {
generate_exception(ctx, EXCP_DSPDIS); if (ctx->insn_flags & ASE_DSP) {
generate_exception(ctx, EXCP_DSPDIS);
} else {
generate_exception(ctx, EXCP_RI);
}
} }
} }
static inline void check_dspr2(DisasContext *ctx) static inline void check_dspr2(DisasContext *ctx)
{ {
if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) {
generate_exception(ctx, EXCP_DSPDIS); if (ctx->insn_flags & ASE_DSP) {
generate_exception(ctx, EXCP_DSPDIS);
} else {
generate_exception(ctx, EXCP_RI);
}
} }
} }