target/i386: Added DR6 and DR7 consistency checks
DR6[63:32] and DR7[63:32] are reserved and need to be zero. (AMD64 Architecture Programmer's Manual, V2, 15.5) Signed-off-by: Lara Lazier <laramglazier@gmail.com> Message-Id: <20210705081802.18960-3-laramglazier@gmail.com> [Ignore for 32-bit builds. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -140,6 +140,8 @@
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#define SVM_MSRPM_SIZE (1ULL << 13)
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#define SVM_IOPM_SIZE ((1ULL << 13) + 1)
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#define SVM_DR_RESERVED_MASK 0xffffffff00000000ULL
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struct QEMU_PACKED vmcb_control_area {
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uint16_t intercept_cr_read;
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uint16_t intercept_cr_write;
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@ -269,7 +269,14 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
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env->dr[6] = x86_ldq_phys(cs,
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env->vm_vmcb + offsetof(struct vmcb, save.dr6));
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/* FIXME: guest state consistency checks */
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#ifdef TARGET_X86_64
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if (env->dr[6] & SVM_DR_RESERVED_MASK) {
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cpu_vmexit(env, SVM_EXIT_ERR, 0, GETPC());
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}
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if (env->dr[7] & SVM_DR_RESERVED_MASK) {
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cpu_vmexit(env, SVM_EXIT_ERR, 0, GETPC());
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}
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#endif
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switch (x86_ldub_phys(cs,
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env->vm_vmcb + offsetof(struct vmcb, control.tlb_ctl))) {
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