util/cacheflush: Fix error generated by clang
When compiling qemu-fuzz-i386 on aarch64 host, clang reported the following error: ../util/cacheflush.c:38:44: error: value size does not match register size specified by the constraint and modifier [-Werror,-Wasm-operand-widths] asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0)); ^ ../util/cacheflush.c:38:24: note: use constraint modifier "w" asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0)); ^~ %w0 Modify the type of save_ctr_el0 to uint64_t to fix it. Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Gan Qixin <ganqixin@huawei.com> Message-Id: <20210115075656.717957-1-ganqixin@huawei.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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@ -32,7 +32,7 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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* We want to save the whole contents of CTR_EL0, so that we
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* We want to save the whole contents of CTR_EL0, so that we
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* have more than the linesize, but also IDC and DIC.
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* have more than the linesize, but also IDC and DIC.
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*/
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*/
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static unsigned int save_ctr_el0;
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static uint64_t save_ctr_el0;
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static void __attribute__((constructor)) init_ctr_el0(void)
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static void __attribute__((constructor)) init_ctr_el0(void)
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{
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{
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asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
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asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
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@ -46,9 +46,9 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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{
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{
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const unsigned CTR_IDC = 1u << 28;
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const unsigned CTR_IDC = 1u << 28;
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const unsigned CTR_DIC = 1u << 29;
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const unsigned CTR_DIC = 1u << 29;
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const unsigned int ctr_el0 = save_ctr_el0;
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const uint64_t ctr_el0 = save_ctr_el0;
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const uintptr_t icache_lsize = 4 << extract32(ctr_el0, 0, 4);
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const uintptr_t icache_lsize = 4 << extract64(ctr_el0, 0, 4);
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const uintptr_t dcache_lsize = 4 << extract32(ctr_el0, 16, 4);
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const uintptr_t dcache_lsize = 4 << extract64(ctr_el0, 16, 4);
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uintptr_t p;
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uintptr_t p;
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/*
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/*
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