From ac70f9767cba3a5966f7eefc102fcda8b3c7d09e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 7 Dec 2020 22:32:49 +0100 Subject: [PATCH] target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As cpu_supports_isa() / cpu_supports_cps_smp() take a 'cpu_type' name argument, rename them cpu_type_supports_FEAT(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201207215257.4004222-2-f4bug@amsat.org> --- hw/mips/boston.c | 4 ++-- hw/mips/malta.c | 4 ++-- target/mips/cpu.h | 4 ++-- target/mips/translate.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 3d40867dc4..16467ea475 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -459,12 +459,12 @@ static void boston_mach_init(MachineState *machine) s = BOSTON(dev); s->mach = machine; - if (!cpu_supports_cps_smp(machine->cpu_type)) { + if (!cpu_type_supports_cps_smp(machine->cpu_type)) { error_report("Boston requires CPUs which support CPS"); exit(1); } - is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64); + is_64b = cpu_type_supports_isa(machine->cpu_type, ISA_MIPS64); object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 5c11eecec1..4651a1055c 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1205,7 +1205,7 @@ static void create_cps(MachineState *ms, MaltaState *s, static void mips_create_cpu(MachineState *ms, MaltaState *s, qemu_irq *cbus_irq, qemu_irq *i8259_irq) { - if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) { + if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) { create_cps(ms, s, cbus_irq, i8259_irq); } else { create_cpu_without_cps(ms, s, cbus_irq, i8259_irq); @@ -1309,7 +1309,7 @@ void mips_malta_init(MachineState *machine) loaderparams.initrd_filename = initrd_filename; kernel_entry = load_kernel(); - if (!cpu_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { + if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { write_bootloader(memory_region_get_ram_ptr(bios), bootloader_run_addr, kernel_entry); } else { diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 23f8c6f96c..9c65c87bf9 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1286,8 +1286,8 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU -bool cpu_supports_cps_smp(const char *cpu_type); -bool cpu_supports_isa(const char *cpu_type, uint64_t isa); +bool cpu_type_supports_cps_smp(const char *cpu_type); +bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); void cpu_set_exception_base(int vp_index, target_ulong address); /* mips_int.c */ diff --git a/target/mips/translate.c b/target/mips/translate.c index c64a1bc42e..b8ed16bb77 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31770,13 +31770,13 @@ void cpu_mips_realize_env(CPUMIPSState *env) mvp_init(env, env->cpu_model); } -bool cpu_supports_cps_smp(const char *cpu_type) +bool cpu_type_supports_cps_smp(const char *cpu_type) { const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; } -bool cpu_supports_isa(const char *cpu_type, uint64_t isa) +bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa) { const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); return (mcc->cpu_def->insn_flags & isa) != 0;