spapr: Set LPCR to current AIL mode when starting a new CPU
TCG does not keep track of AIL mode in a central place, it's based on the current LPCR[AIL] bits. Synchronize the new CPU's LPCR to the current LPCR in rtas_start_cpu(), similarly to the way the ILE bit is synchronized. Open-code the ILE setting as well now that the caller's LPCR is available directly, there is no need for the indirection. Without this, under both TCG and KVM, adding a POWER8/9/10 class CPU with a new core ID after a modern Linux has booted results in the new CPU's LPCR missing the LPCR[AIL]=0b11 setting that the other CPUs have. This can cause crashes and unexpected behaviour. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20210526091626.3388262-3-npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -132,8 +132,8 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr,
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target_ulong id, start, r3;
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PowerPCCPU *newcpu;
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CPUPPCState *env;
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PowerPCCPUClass *pcc;
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target_ulong lpcr;
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target_ulong caller_lpcr;
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if (nargs != 3 || nret != 1) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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@ -152,7 +152,6 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr,
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}
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env = &newcpu->env;
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pcc = POWERPC_CPU_GET_CLASS(newcpu);
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if (!CPU(newcpu)->halted) {
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rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
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@ -164,10 +163,15 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr,
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env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME);
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hreg_compute_hflags(env);
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caller_lpcr = callcpu->env.spr[SPR_LPCR];
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lpcr = env->spr[SPR_LPCR];
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if (!pcc->interrupts_big_endian(callcpu)) {
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lpcr |= LPCR_ILE;
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}
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/* Set ILE the same way */
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lpcr = (lpcr & ~LPCR_ILE) | (caller_lpcr & LPCR_ILE);
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/* Set AIL the same way */
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lpcr = (lpcr & ~LPCR_AIL) | (caller_lpcr & LPCR_AIL);
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if (env->mmu_model == POWERPC_MMU_3_00) {
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/*
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* New cpus are expected to start in the same radix/hash mode
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