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spapr: Set LPCR to current AIL mode when starting a new CPU

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TCG does not keep track of AIL mode in a central place, it's based on
the current LPCR[AIL] bits. Synchronize the new CPU's LPCR to the
current LPCR in rtas_start_cpu(), similarly to the way the ILE bit is
synchronized.

Open-code the ILE setting as well now that the caller's LPCR is
available directly, there is no need for the indirection.

Without this, under both TCG and KVM, adding a POWER8/9/10 class CPU
with a new core ID after a modern Linux has booted results in the new
CPU's LPCR missing the LPCR[AIL]=0b11 setting that the other CPUs have.
This can cause crashes and unexpected behaviour.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20210526091626.3388262-3-npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Nicholas Piggin 2021-05-26 19:16:25 +10:00 committed by David Gibson
parent 7be3bf6c84
commit ac559ecbea
1 changed files with 9 additions and 5 deletions
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14
hw/ppc/spapr_rtas.c
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@ -132,8 +132,8 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr,
target_ulong id, start, r3; target_ulong id, start, r3;
PowerPCCPU *newcpu; PowerPCCPU *newcpu;
CPUPPCState *env; CPUPPCState *env;
PowerPCCPUClass *pcc;
target_ulong lpcr; target_ulong lpcr;
target_ulong caller_lpcr;
if (nargs != 3 || nret != 1) { if (nargs != 3 || nret != 1) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
@ -152,7 +152,6 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr,
} }
env = &newcpu->env; env = &newcpu->env;
pcc = POWERPC_CPU_GET_CLASS(newcpu);
if (!CPU(newcpu)->halted) { if (!CPU(newcpu)->halted) {
rtas_st(rets, 0, RTAS_OUT_HW_ERROR); rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
@ -164,10 +163,15 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr,
env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME); env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME);
hreg_compute_hflags(env); hreg_compute_hflags(env);
caller_lpcr = callcpu->env.spr[SPR_LPCR];
lpcr = env->spr[SPR_LPCR]; lpcr = env->spr[SPR_LPCR];
if (!pcc->interrupts_big_endian(callcpu)) {
lpcr |= LPCR_ILE; /* Set ILE the same way */
} lpcr = (lpcr & ~LPCR_ILE) | (caller_lpcr & LPCR_ILE);
/* Set AIL the same way */
lpcr = (lpcr & ~LPCR_AIL) | (caller_lpcr & LPCR_AIL);
if (env->mmu_model == POWERPC_MMU_3_00) { if (env->mmu_model == POWERPC_MMU_3_00) {
/* /*
* New cpus are expected to start in the same radix/hash mode * New cpus are expected to start in the same radix/hash mode