target/riscv: Implement AIA IMSIC interface CSRs
The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-16-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel
Alistair Francis
parent
d1ceff405a
commit
ac4b0302b0
@ -942,6 +942,16 @@ static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
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return CSR_VSISELECT;
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case CSR_SIREG:
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return CSR_VSIREG;
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case CSR_SSETEIPNUM:
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return CSR_VSSETEIPNUM;
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case CSR_SCLREIPNUM:
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return CSR_VSCLREIPNUM;
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case CSR_SSETEIENUM:
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return CSR_VSSETEIENUM;
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case CSR_SCLREIENUM:
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return CSR_VSCLREIENUM;
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case CSR_STOPEI:
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return CSR_VSTOPEI;
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default:
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return csrno;
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};
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@ -1094,6 +1104,178 @@ done:
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return RISCV_EXCP_NONE;
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}
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static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong *val,
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target_ulong new_val, target_ulong wr_mask)
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{
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int ret = -EINVAL;
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bool set, pend, virt;
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target_ulong priv, isel, vgein, xlen, nval, wmask;
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/* Translate CSR number for VS-mode */
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csrno = aia_xlate_vs_csrno(env, csrno);
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/* Decode register details from CSR number */
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virt = set = pend = false;
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switch (csrno) {
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case CSR_MSETEIPNUM:
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priv = PRV_M;
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set = true;
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pend = true;
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break;
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case CSR_MCLREIPNUM:
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priv = PRV_M;
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pend = true;
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break;
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case CSR_MSETEIENUM:
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priv = PRV_M;
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set = true;
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break;
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case CSR_MCLREIENUM:
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priv = PRV_M;
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break;
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case CSR_SSETEIPNUM:
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priv = PRV_S;
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set = true;
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pend = true;
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break;
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case CSR_SCLREIPNUM:
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priv = PRV_S;
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pend = true;
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break;
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case CSR_SSETEIENUM:
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priv = PRV_S;
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set = true;
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break;
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case CSR_SCLREIENUM:
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priv = PRV_S;
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break;
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case CSR_VSSETEIPNUM:
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priv = PRV_S;
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virt = true;
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set = true;
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pend = true;
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break;
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case CSR_VSCLREIPNUM:
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priv = PRV_S;
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virt = true;
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pend = true;
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break;
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case CSR_VSSETEIENUM:
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priv = PRV_S;
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virt = true;
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set = true;
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break;
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case CSR_VSCLREIENUM:
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priv = PRV_S;
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virt = true;
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break;
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default:
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goto done;
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};
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/* IMSIC CSRs only available when machine implements IMSIC. */
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if (!env->aia_ireg_rmw_fn[priv]) {
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goto done;
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}
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/* Find the selected guest interrupt file */
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vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
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/* Selected guest interrupt file should be valid */
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if (virt && (!vgein || env->geilen < vgein)) {
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goto done;
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}
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/* Set/Clear CSRs always read zero */
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if (val) {
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*val = 0;
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}
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if (wr_mask) {
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/* Get interrupt number */
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new_val &= wr_mask;
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/* Find target interrupt pending/enable register */
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xlen = riscv_cpu_mxl_bits(env);
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isel = (new_val / xlen);
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isel *= (xlen / IMSIC_EIPx_BITS);
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isel += (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0;
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/* Find the interrupt bit to be set/clear */
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wmask = ((target_ulong)1) << (new_val % xlen);
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nval = (set) ? wmask : 0;
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/* Call machine specific IMSIC register emulation */
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ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
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AIA_MAKE_IREG(isel, priv, virt,
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vgein, xlen),
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NULL, nval, wmask);
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} else {
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ret = 0;
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}
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done:
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if (ret) {
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return (riscv_cpu_virt_enabled(env) && virt) ?
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RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
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}
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return RISCV_EXCP_NONE;
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}
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static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val,
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target_ulong new_val, target_ulong wr_mask)
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{
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bool virt;
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int ret = -EINVAL;
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target_ulong priv, vgein;
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/* Translate CSR number for VS-mode */
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csrno = aia_xlate_vs_csrno(env, csrno);
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/* Decode register details from CSR number */
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virt = false;
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switch (csrno) {
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case CSR_MTOPEI:
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priv = PRV_M;
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break;
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case CSR_STOPEI:
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priv = PRV_S;
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break;
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case CSR_VSTOPEI:
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priv = PRV_S;
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virt = true;
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break;
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default:
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goto done;
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};
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/* IMSIC CSRs only available when machine implements IMSIC. */
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if (!env->aia_ireg_rmw_fn[priv]) {
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goto done;
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}
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/* Find the selected guest interrupt file */
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vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
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/* Selected guest interrupt file should be valid */
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if (virt && (!vgein || env->geilen < vgein)) {
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goto done;
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}
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/* Call machine specific IMSIC register emulation for TOPEI */
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ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
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AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein,
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riscv_cpu_mxl_bits(env)),
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val, new_val, wr_mask);
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done:
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if (ret) {
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return (riscv_cpu_virt_enabled(env) && virt) ?
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RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
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}
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_mtvec(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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@ -2930,6 +3112,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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/* Machine-Level Interrupts (AIA) */
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[CSR_MTOPI] = { "mtopi", aia_any, read_mtopi },
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/* Machine-Level IMSIC Interface (AIA) */
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[CSR_MSETEIPNUM] = { "mseteipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
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[CSR_MCLREIPNUM] = { "mclreipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
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[CSR_MSETEIENUM] = { "mseteienum", aia_any, NULL, NULL, rmw_xsetclreinum },
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[CSR_MCLREIENUM] = { "mclreienum", aia_any, NULL, NULL, rmw_xsetclreinum },
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[CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei },
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/* Virtual Interrupts for Supervisor Level (AIA) */
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[CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore },
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[CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore },
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@ -2966,6 +3155,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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/* Supervisor-Level Interrupts (AIA) */
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[CSR_STOPI] = { "stopi", aia_smode, read_stopi },
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/* Supervisor-Level IMSIC Interface (AIA) */
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[CSR_SSETEIPNUM] = { "sseteipnum", aia_smode, NULL, NULL, rmw_xsetclreinum },
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[CSR_SCLREIPNUM] = { "sclreipnum", aia_smode, NULL, NULL, rmw_xsetclreinum },
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[CSR_SSETEIENUM] = { "sseteienum", aia_smode, NULL, NULL, rmw_xsetclreinum },
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[CSR_SCLREIENUM] = { "sclreienum", aia_smode, NULL, NULL, rmw_xsetclreinum },
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[CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei },
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/* Supervisor-Level High-Half CSRs (AIA) */
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[CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
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[CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
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@ -3013,6 +3209,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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/* VS-Level Interrupts (H-extension with AIA) */
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[CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
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/* VS-Level IMSIC Interface (H-extension with AIA) */
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[CSR_VSSETEIPNUM] = { "vsseteipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
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[CSR_VSCLREIPNUM] = { "vsclreipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
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[CSR_VSSETEIENUM] = { "vsseteienum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
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[CSR_VSCLREIENUM] = { "vsclreienum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
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[CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei },
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/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
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[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
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[CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore },
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