target/loongarch: Implement xvfrstp
This patch includes: - XVFRSTP[I].{B/H}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-46-gaosong@loongson.cn>
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@ -2235,6 +2235,11 @@ INSN_LASX(xvbitrevi_h, vv_i)
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INSN_LASX(xvbitrevi_w, vv_i)
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INSN_LASX(xvbitrevi_w, vv_i)
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INSN_LASX(xvbitrevi_d, vv_i)
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INSN_LASX(xvbitrevi_d, vv_i)
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INSN_LASX(xvfrstp_b, vvv)
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INSN_LASX(xvfrstp_h, vvv)
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INSN_LASX(xvfrstpi_b, vv_i)
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INSN_LASX(xvfrstpi_h, vv_i)
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INSN_LASX(xvreplgr2vr_b, vr)
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INSN_LASX(xvreplgr2vr_b, vr)
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INSN_LASX(xvreplgr2vr_h, vr)
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INSN_LASX(xvreplgr2vr_h, vr)
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INSN_LASX(xvreplgr2vr_w, vr)
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INSN_LASX(xvreplgr2vr_w, vr)
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@ -4300,6 +4300,10 @@ TRANS(vfrstp_b, LSX, gen_vvv, gen_helper_vfrstp_b)
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TRANS(vfrstp_h, LSX, gen_vvv, gen_helper_vfrstp_h)
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TRANS(vfrstp_h, LSX, gen_vvv, gen_helper_vfrstp_h)
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TRANS(vfrstpi_b, LSX, gen_vv_i, gen_helper_vfrstpi_b)
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TRANS(vfrstpi_b, LSX, gen_vv_i, gen_helper_vfrstpi_b)
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TRANS(vfrstpi_h, LSX, gen_vv_i, gen_helper_vfrstpi_h)
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TRANS(vfrstpi_h, LSX, gen_vv_i, gen_helper_vfrstpi_h)
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TRANS(xvfrstp_b, LASX, gen_xxx, gen_helper_vfrstp_b)
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TRANS(xvfrstp_h, LASX, gen_xxx, gen_helper_vfrstp_h)
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TRANS(xvfrstpi_b, LASX, gen_xx_i, gen_helper_vfrstpi_b)
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TRANS(xvfrstpi_h, LASX, gen_xx_i, gen_helper_vfrstpi_h)
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TRANS(vfadd_s, LSX, gen_vvv_ptr, gen_helper_vfadd_s)
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TRANS(vfadd_s, LSX, gen_vvv_ptr, gen_helper_vfadd_s)
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TRANS(vfadd_d, LSX, gen_vvv_ptr, gen_helper_vfadd_d)
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TRANS(vfadd_d, LSX, gen_vvv_ptr, gen_helper_vfadd_d)
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@ -1811,6 +1811,11 @@ xvbitrevi_h 0111 01110001 10000 1 .... ..... ..... @vv_ui4
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xvbitrevi_w 0111 01110001 10001 ..... ..... ..... @vv_ui5
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xvbitrevi_w 0111 01110001 10001 ..... ..... ..... @vv_ui5
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xvbitrevi_d 0111 01110001 1001 ...... ..... ..... @vv_ui6
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xvbitrevi_d 0111 01110001 1001 ...... ..... ..... @vv_ui6
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xvfrstp_b 0111 01010010 10110 ..... ..... ..... @vvv
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xvfrstp_h 0111 01010010 10111 ..... ..... ..... @vvv
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xvfrstpi_b 0111 01101001 10100 ..... ..... ..... @vv_ui5
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xvfrstpi_h 0111 01101001 10101 ..... ..... ..... @vv_ui5
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xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
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xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
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xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
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xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
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xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
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xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
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@ -2369,18 +2369,22 @@ DO_BITI(vbitrevi_d, 64, UD, DO_BITREV)
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#define VFRSTP(NAME, BIT, MASK, E) \
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#define VFRSTP(NAME, BIT, MASK, E) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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{ \
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int i, m; \
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int i, j, m, ofs; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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VReg *Vk = (VReg *)vk; \
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int oprsz = simd_oprsz(desc); \
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\
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\
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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ofs = LSX_LEN / BIT; \
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if (Vj->E(i) < 0) { \
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for (i = 0; i < oprsz / 16; i++) { \
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break; \
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m = Vk->E(i * ofs) & MASK; \
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for (j = 0; j < ofs; j++) { \
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if (Vj->E(j + ofs * i) < 0) { \
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break; \
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} \
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} \
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} \
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Vd->E(m + i * ofs) = j; \
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} \
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} \
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m = Vk->E(0) & MASK; \
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Vd->E(m) = i; \
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}
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}
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VFRSTP(vfrstp_b, 8, 0xf, B)
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VFRSTP(vfrstp_b, 8, 0xf, B)
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@ -2389,17 +2393,21 @@ VFRSTP(vfrstp_h, 16, 0x7, H)
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#define VFRSTPI(NAME, BIT, E) \
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#define VFRSTPI(NAME, BIT, E) \
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void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
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void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
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{ \
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{ \
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int i, m; \
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int i, j, m, ofs; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vj = (VReg *)vj; \
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int oprsz = simd_oprsz(desc); \
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\
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\
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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ofs = LSX_LEN / BIT; \
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if (Vj->E(i) < 0) { \
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m = imm % ofs; \
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break; \
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for (i = 0; i < oprsz / 16; i++) { \
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for (j = 0; j < ofs; j++) { \
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if (Vj->E(j + ofs * i) < 0) { \
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break; \
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} \
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} \
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} \
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Vd->E(m + i * ofs) = j; \
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} \
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} \
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m = imm % (LSX_LEN/BIT); \
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Vd->E(m) = i; \
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}
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}
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VFRSTPI(vfrstpi_b, 8, B)
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VFRSTPI(vfrstpi_b, 8, B)
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