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target/loongarch: Implement xvfrstp

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This patch includes:
- XVFRSTP[I].{B/H}.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-46-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-09-14 10:26:33 +08:00
parent 1b3e242f72
commit abee168ea3
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
4 changed files with 34 additions and 12 deletions
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5
target/loongarch/disas.c
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@ -2235,6 +2235,11 @@ INSN_LASX(xvbitrevi_h, vv_i)
INSN_LASX(xvbitrevi_w, vv_i)
INSN_LASX(xvbitrevi_d, vv_i)
INSN_LASX(xvfrstp_b, vvv)
INSN_LASX(xvfrstp_h, vvv)
INSN_LASX(xvfrstpi_b, vv_i)
INSN_LASX(xvfrstpi_h, vv_i)
INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)

4
target/loongarch/insn_trans/trans_vec.c.inc
View File

@ -4300,6 +4300,10 @@ TRANS(vfrstp_b, LSX, gen_vvv, gen_helper_vfrstp_b)
TRANS(vfrstp_h, LSX, gen_vvv, gen_helper_vfrstp_h)
TRANS(vfrstpi_b, LSX, gen_vv_i, gen_helper_vfrstpi_b)
TRANS(vfrstpi_h, LSX, gen_vv_i, gen_helper_vfrstpi_h)
TRANS(xvfrstp_b, LASX, gen_xxx, gen_helper_vfrstp_b)
TRANS(xvfrstp_h, LASX, gen_xxx, gen_helper_vfrstp_h)
TRANS(xvfrstpi_b, LASX, gen_xx_i, gen_helper_vfrstpi_b)
TRANS(xvfrstpi_h, LASX, gen_xx_i, gen_helper_vfrstpi_h)
TRANS(vfadd_s, LSX, gen_vvv_ptr, gen_helper_vfadd_s)
TRANS(vfadd_d, LSX, gen_vvv_ptr, gen_helper_vfadd_d)

5
target/loongarch/insns.decode
View File

@ -1811,6 +1811,11 @@ xvbitrevi_h 0111 01110001 10000 1 .... ..... ..... @vv_ui4
xvbitrevi_w 0111 01110001 10001 ..... ..... ..... @vv_ui5
xvbitrevi_d 0111 01110001 1001 ...... ..... ..... @vv_ui6
xvfrstp_b 0111 01010010 10110 ..... ..... ..... @vvv
xvfrstp_h 0111 01010010 10111 ..... ..... ..... @vvv
xvfrstpi_b 0111 01101001 10100 ..... ..... ..... @vv_ui5
xvfrstpi_h 0111 01101001 10101 ..... ..... ..... @vv_ui5
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr

32
target/loongarch/vec_helper.c
View File

@ -2369,18 +2369,22 @@ DO_BITI(vbitrevi_d, 64, UD, DO_BITREV)
#define VFRSTP(NAME, BIT, MASK, E) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i, m; \
int i, j, m, ofs; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < LSX_LEN/BIT; i++) { \
if (Vj->E(i) < 0) { \
break; \
ofs = LSX_LEN / BIT; \
for (i = 0; i < oprsz / 16; i++) { \
m = Vk->E(i * ofs) & MASK; \
for (j = 0; j < ofs; j++) { \
if (Vj->E(j + ofs * i) < 0) { \
break; \
} \
} \
Vd->E(m + i * ofs) = j; \
} \
m = Vk->E(0) & MASK; \
Vd->E(m) = i; \
}
VFRSTP(vfrstp_b, 8, 0xf, B)
@ -2389,17 +2393,21 @@ VFRSTP(vfrstp_h, 16, 0x7, H)
#define VFRSTPI(NAME, BIT, E) \
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
{ \
int i, m; \
int i, j, m, ofs; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < LSX_LEN/BIT; i++) { \
if (Vj->E(i) < 0) { \
break; \
ofs = LSX_LEN / BIT; \
m = imm % ofs; \
for (i = 0; i < oprsz / 16; i++) { \
for (j = 0; j < ofs; j++) { \
if (Vj->E(j + ofs * i) < 0) { \
break; \
} \
} \
Vd->E(m + i * ofs) = j; \
} \
m = imm % (LSX_LEN/BIT); \
Vd->E(m) = i; \
}
VFRSTPI(vfrstpi_b, 8, B)