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target/mips: Add missing 'break' for a case of MTHC0 handling

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This was found by GCC 8.3 static analysis.

Fixes: 5fb2dcd179

Reported-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1563220847-14630-3-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic 2019-07-15 22:00:44 +02:00
parent 5ea8ec2fcf
commit ab8c34105a
1 changed files with 1 additions and 0 deletions
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target/mips/translate.c
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@ -6745,6 +6745,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
break;
case CP0_REGISTER_17:
switch (sel) {
case 0: