target/arm: Introduce tlbi_aa64_get_range
Merge tlbi_aa64_range_get_length and tlbi_aa64_range_get_base, returning a structure containing both results. Pass in the ARMMMUIdx, rather than the digested two_ranges boolean. This is in preparation for FEAT_LPA2, where the interpretation of 'value' depends on the effective value of DS for the regime. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220301215958.157011-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -4511,70 +4511,60 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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#ifdef TARGET_AARCH64
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#ifdef TARGET_AARCH64
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static uint64_t tlbi_aa64_range_get_length(CPUARMState *env,
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typedef struct {
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uint64_t base;
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uint64_t length;
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} TLBIRange;
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static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
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uint64_t value)
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uint64_t value)
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{
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{
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unsigned int page_shift;
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unsigned int page_size_granule, page_shift, num, scale, exponent;
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unsigned int page_size_granule;
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TLBIRange ret = { };
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uint64_t num;
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uint64_t scale;
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uint64_t exponent;
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uint64_t length;
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num = extract64(value, 39, 5);
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scale = extract64(value, 44, 2);
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page_size_granule = extract64(value, 46, 2);
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page_size_granule = extract64(value, 46, 2);
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if (page_size_granule == 0) {
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if (page_size_granule == 0) {
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
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page_size_granule);
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page_size_granule);
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return 0;
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return ret;
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}
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}
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page_shift = (page_size_granule - 1) * 2 + 12;
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page_shift = (page_size_granule - 1) * 2 + 12;
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num = extract64(value, 39, 5);
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scale = extract64(value, 44, 2);
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exponent = (5 * scale) + 1;
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exponent = (5 * scale) + 1;
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length = (num + 1) << (exponent + page_shift);
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return length;
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ret.length = (num + 1) << (exponent + page_shift);
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}
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static uint64_t tlbi_aa64_range_get_base(CPUARMState *env, uint64_t value,
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if (regime_has_2_ranges(mmuidx)) {
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bool two_ranges)
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ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS;
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{
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/* TODO: ARMv8.7 FEAT_LPA2 */
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uint64_t pageaddr;
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if (two_ranges) {
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pageaddr = sextract64(value, 0, 37) << TARGET_PAGE_BITS;
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} else {
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} else {
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pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS;
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ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS;
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}
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}
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return pageaddr;
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return ret;
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}
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}
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static void do_rvae_write(CPUARMState *env, uint64_t value,
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static void do_rvae_write(CPUARMState *env, uint64_t value,
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int idxmap, bool synced)
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int idxmap, bool synced)
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{
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{
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ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap);
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ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap);
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bool two_ranges = regime_has_2_ranges(one_idx);
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TLBIRange range;
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uint64_t baseaddr, length;
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int bits;
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int bits;
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baseaddr = tlbi_aa64_range_get_base(env, value, two_ranges);
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range = tlbi_aa64_get_range(env, one_idx, value);
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length = tlbi_aa64_range_get_length(env, value);
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bits = tlbbits_for_regime(env, one_idx, range.base);
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bits = tlbbits_for_regime(env, one_idx, baseaddr);
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if (synced) {
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if (synced) {
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tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env),
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tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env),
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baseaddr,
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range.base,
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length,
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range.length,
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idxmap,
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idxmap,
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bits);
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bits);
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} else {
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} else {
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tlb_flush_range_by_mmuidx(env_cpu(env), baseaddr,
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tlb_flush_range_by_mmuidx(env_cpu(env), range.base,
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length, idxmap, bits);
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range.length, idxmap, bits);
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}
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}
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}
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}
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