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target-tilegx: Implement v?int_* instructions.

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Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1443956491-26850-2-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Chen Gang 2015-10-04 19:01:26 +08:00 committed by Richard Henderson
parent 78affcb798
commit aaf893a6ad
3 changed files with 67 additions and 0 deletions
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5
target-tilegx/helper.h
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@ -10,6 +10,11 @@ DEF_HELPER_FLAGS_3(cmula, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_3(cmulaf, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(cmulaf, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_4(cmul2, TCG_CALL_NO_RWG_SE, i64, i64, i64, int, int) DEF_HELPER_FLAGS_4(cmul2, TCG_CALL_NO_RWG_SE, i64, i64, i64, int, int)
DEF_HELPER_FLAGS_2(v1int_h, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1int_l, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v2int_h, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v2int_l, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1multu, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1multu, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)

48
target-tilegx/simd_helper.c
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@ -100,3 +100,51 @@ uint64_t helper_v2shrs(uint64_t a, uint64_t b)
} }
return r; return r;
} }
uint64_t helper_v1int_h(uint64_t a, uint64_t b)
{
uint64_t r = 0;
int i;
for (i = 0; i < 32; i += 8) {
r = deposit64(r, 2 * i + 8, 8, extract64(a, i + 32, 8));
r = deposit64(r, 2 * i, 8, extract64(b, i + 32, 8));
}
return r;
}
uint64_t helper_v1int_l(uint64_t a, uint64_t b)
{
uint64_t r = 0;
int i;
for (i = 0; i < 32; i += 8) {
r = deposit64(r, 2 * i + 8, 8, extract64(a, i, 8));
r = deposit64(r, 2 * i, 8, extract64(b, i, 8));
}
return r;
}
uint64_t helper_v2int_h(uint64_t a, uint64_t b)
{
uint64_t r = 0;
int i;
for (i = 0; i < 32; i += 16) {
r = deposit64(r, 2 * i + 16, 16, extract64(a, i + 32, 16));
r = deposit64(r, 2 * i, 16, extract64(b, i + 32, 16));
}
return r;
}
uint64_t helper_v2int_l(uint64_t a, uint64_t b)
{
uint64_t r = 0;
int i;
for (i = 0; i < 32; i += 16) {
r = deposit64(r, 2 * i + 16, 16, extract64(a, i, 16));
r = deposit64(r, 2 * i, 16, extract64(b, i, 16));
}
return r;
}

14
target-tilegx/translate.c
View File

@ -1260,10 +1260,17 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(V1DOTPUS, 0, X0): case OE_RRR(V1DOTPUS, 0, X0):
case OE_RRR(V1DOTPU, 0, X0): case OE_RRR(V1DOTPU, 0, X0):
case OE_RRR(V1DOTP, 0, X0): case OE_RRR(V1DOTP, 0, X0):
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V1INT_H, 0, X0): case OE_RRR(V1INT_H, 0, X0):
case OE_RRR(V1INT_H, 0, X1): case OE_RRR(V1INT_H, 0, X1):
gen_helper_v1int_h(tdest, tsrca, tsrcb);
mnemonic = "v1int_h";
break;
case OE_RRR(V1INT_L, 0, X0): case OE_RRR(V1INT_L, 0, X0):
case OE_RRR(V1INT_L, 0, X1): case OE_RRR(V1INT_L, 0, X1):
gen_helper_v1int_l(tdest, tsrca, tsrcb);
mnemonic = "v1int_l";
break;
case OE_RRR(V1MAXU, 0, X0): case OE_RRR(V1MAXU, 0, X0):
case OE_RRR(V1MAXU, 0, X1): case OE_RRR(V1MAXU, 0, X1):
case OE_RRR(V1MINU, 0, X0): case OE_RRR(V1MINU, 0, X0):
@ -1329,10 +1336,17 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(V2CMPNE, 0, X1): case OE_RRR(V2CMPNE, 0, X1):
case OE_RRR(V2DOTPA, 0, X0): case OE_RRR(V2DOTPA, 0, X0):
case OE_RRR(V2DOTP, 0, X0): case OE_RRR(V2DOTP, 0, X0):
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V2INT_H, 0, X0): case OE_RRR(V2INT_H, 0, X0):
case OE_RRR(V2INT_H, 0, X1): case OE_RRR(V2INT_H, 0, X1):
gen_helper_v2int_h(tdest, tsrca, tsrcb);
mnemonic = "v2int_h";
break;
case OE_RRR(V2INT_L, 0, X0): case OE_RRR(V2INT_L, 0, X0):
case OE_RRR(V2INT_L, 0, X1): case OE_RRR(V2INT_L, 0, X1):
gen_helper_v2int_l(tdest, tsrca, tsrcb);
mnemonic = "v2int_l";
break;
case OE_RRR(V2MAXS, 0, X0): case OE_RRR(V2MAXS, 0, X0):
case OE_RRR(V2MAXS, 0, X1): case OE_RRR(V2MAXS, 0, X1):
case OE_RRR(V2MINS, 0, X0): case OE_RRR(V2MINS, 0, X0):