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target/arm: Use smin/smax for do_sat_addsub_32

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The operation we're performing with the movcond
is either min/max depending on cond -- simplify.
Use tcg_constant_i64 while we're at it.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-17 10:43:46 -07:00 committed by Peter Maydell
parent d9b47e97e7
commit aa5b0b29b1
1 changed files with 2 additions and 7 deletions
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9
target/arm/translate-sve.c
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@ -1916,8 +1916,6 @@ static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a)
static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
{ {
int64_t ibound; int64_t ibound;
TCGv_i64 bound;
TCGCond cond;
/* Use normal 64-bit arithmetic to detect 32-bit overflow. */ /* Use normal 64-bit arithmetic to detect 32-bit overflow. */
if (u) { if (u) {
@ -1928,15 +1926,12 @@ static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
if (d) { if (d) {
tcg_gen_sub_i64(reg, reg, val); tcg_gen_sub_i64(reg, reg, val);
ibound = (u ? 0 : INT32_MIN); ibound = (u ? 0 : INT32_MIN);
cond = TCG_COND_LT; tcg_gen_smax_i64(reg, reg, tcg_constant_i64(ibound));
} else { } else {
tcg_gen_add_i64(reg, reg, val); tcg_gen_add_i64(reg, reg, val);
ibound = (u ? UINT32_MAX : INT32_MAX); ibound = (u ? UINT32_MAX : INT32_MAX);
cond = TCG_COND_GT; tcg_gen_smin_i64(reg, reg, tcg_constant_i64(ibound));
} }
bound = tcg_const_i64(ibound);
tcg_gen_movcond_i64(cond, reg, reg, bound, bound, reg);
tcg_temp_free_i64(bound);
} }
/* Similarly with 64-bit values. */ /* Similarly with 64-bit values. */